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13:30 |
A1-1 |
Novel VLSI Design of Circular-Carry-Select (CCS) Based Diminished-One
Modulo 2n+1 Adder |
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PDF |
Su-Hon Lin, Ming-Hwa Sheu, Kuang-Hui Wang, Jun-Jie Zhu, and Si-Ying Chen,
國立雲林科技大學 |
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13:45 |
A1-2 |
Self-Aware Medium-Grained Adaptive Power Control Using Current
Monitoring Technique |
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PDF |
Wei-Chih Hsieh and Wei Hwang, 國立交通大學 |
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14:00 |
A1-3 |
Post-Chip Adjustable Low Power Delay Element |
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PDF |
Jung-Lin Yang and Chih-Wei Chao, 南台科技大學 |
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14:15 |
A1-4 |
A High-Resolution All-Digital Phase-Locked Loop with its Application to
Built-In Speed Grading for Memory |
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PDF |
Hsuan-Jung Hsu, Chun-Chieh Tu, and Shi-Yu Huang , 國立清華大學 |
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14:30 |
A1-5 |
All-Digital PLL Using Bulk-Controlled Varactor and Pulse-Based DCO |
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PDF |
Hong-Yi Huang and Jen-Chieh Liu, 國立台北大學 |
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14:45 |
A1-6 |
A Conditional Isolation Technique for Low-Power and High-speed Wide
Domino Gates |
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PDF |
Wei-Hao Chiu and How-Rern Lin, 大葉大學 |