|
13:30 |
B1-1 |
Novel Low-Power Bus Coding Method for Crosstalk Noise Reduction |
| |
PDF |
Chia-Hao Fang and Chih-Peng Fan, 國立中興大學 |
|
13:45 |
B1-2 |
Reconfigurable Hardware Module Sequencer for Dynamically Partially
Reconfigurable Systems |
| |
PDF |
Chin-Chieh Hung and Pao-Ann Hsiung, 國立中正大學 |
|
14:00 |
B1-3 |
Implementing an FPGA Baseband Multipath Fading Channel Emulator Using
High-Level Modular Design |
| |
PDF |
Jeng-Kuang Hwang*, Kuei-Horng Lin, Jeng-Da Li, and Juinn-Horng Deng,
元智大學 |
|
14:15 |
B1-4 |
HW/SW Co-Design of a Multi-Threaded Virtual Machine for a Scalable NoC
Platform |
| |
PDF |
李昀隆、陳泳超、周哲民, 國立成功大學 |
|
14:30 |
B1-5 |
High Speed and Low Cost Implementations in Mix-Column/InvMix-Column |
| |
PDF |
Chung-Yi Li, Chih-Feng Chien, and Tsin-Yuan Chang, 國立清華大學 |
|
14:45 |
B1-6 |
Combined Decoding and Flexible Transform Designs for Effective H.264/AVC
Decoders |
| |
PDF |
Yi-Chih Chao, Shih-Tse Wei, Jar-Ferr Yang, and Bin-Da Liu, 國立成功大學 |