TECHNICAL PROGRAM

Session

B2
Day

08/09
Time

10:00-11:30
Chair
黃錫瑜 教授
國立清華大學
Room

305

Memory/CPU/DSP Cores

10:00 B2-1  A Protocol-Reconfigurable Double-Layer External Memory Management for H.264/AVC Decoder
  PDF Chang-Hsuan Chang, Ming-Hung Chang, and Wei Hwang, 國立交通大學  
10:15 B2-2  A Energy-Efficient 256X144 TCAM Design
  PDF Wen-Yen Liu, Po-Tsang Huang, and Wei Hwang, 國立交通大學  
10:30 B2-3  Energy-Efficient and High-Performance Power Gating in Microprocessor Functional Units
  PDF Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, and Chingwei Yeh, 國立中正大學  
10:45 B2-4  A Mini Stereo Digital Audio Processor Design
  PDF Po-Yu Kuo, Dian Zhou, and Zhi-Ming Lin, 德州大學達拉斯分校  
11:00 B2-5  Adaptive Sensing Control in SRAM Design Using Per-Column Timing Tracking Scheme
  PDF Ya-Chun Lai, Ming-Yi Chang, and Shi-Yu Huang, 國立清華大學  
11:15 B2-6  Compact Dual-Core Architecture
  PDF Jih-Ching Chiu and Yu-Liang Chou, 國立中山大學