Wireline Communication Circuits

13:30	D1-1	A Quarter-Rate 2.56/3.2Gbps 16/20:1 SERDES Interface in 0.18μm CMOS technology
	PDF	Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, YarSun Hsu, Ming-Hao Lu, Ping-Lin Yang, Fan-Ta Chen, You-Hung Li, Yu-Hao Hsu, and Min-Sheng Kao, 國立清華大學
13:45	D1-2	A Low Power Tree-Type Multiplexer with Embedded Timing Skew Switch
	PDF	HungWen Lu, 國立中央大學
14:00	D1-3	Transimpedance Amplifier with Enlarged Input Capacitance Tolerance for Optical Receiver
	PDF	Jiann-Jiun Lu and Chia-Ming Tsai, 國立交通大學
14:15	D1-4	A Low-jitter Phase-rotation Spread Spectrum Clock Generator for Serial ATA 6Gbps Clock and Data Recovery
	PDF	Chi- Hsien Lin, Yen-Ying Huang, Shu-Rung Li, Yuan-Pu Cheng, and Shyh- Jye Jou, 國立交通大學
14:30	D1-5	A 2.5 Gbps CMOS Fully Integrated Optical Receicer with Lateral PIN Detector
	PDF	Wei-Zen Chen and Shih-Hao Huang, 國立交通大學
14:45	D1-6	Inductorless CMOS Receiver Front-End Circuits for 10-Gbs Optical Communications
	PDF	Chih-Hao Chen, 淡江大學