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10:00 |
D3-1 |
Stability Analysis of Fourth-Order Charge-Pump PLLs using Linearized
Discrete-Time Models |
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PDF |
Chia-Yu Yao, Chun-Te Hsu, and Chih-Chun Hsieh, 國立台灣科技大學 |
|
10:15 |
D3-2 |
A Low Jitter 2.5-GHz Self-Calibration PLL |
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PDF |
鄭國興、蔡玉章、洪凱尉, 國立中央大學 |
|
10:30 |
D3-3 |
A CMOS-MEMS Frequency Adaptive Resonator with Multiple Electrostatic
Electrodes Driving. |
| |
PDF |
J. C. Chiou and L. J. Shieh, 國立交通大學 |
|
10:45 |
D3-4 |
An Efficient BMCS Approach to Accurately Predict Process Variation
Effects of PLL Circuits |
| |
PDF |
Chin-Cheng Kuo, Meng-Jung Lee, I-Ching Tsai, Chien-Nan Jimmy Liu, and
Ching-Ji Huang, 國立中央大學 |
|
11:00 |
D3-5 |
A Low Power Wide Range Duty Cycle Corrector Based on Pulse
Shrinking/Stretching Mechanism |
| |
PDF |
Poki Chen, Shi-Wei Chen, and Juan-Shan Lai, 國立台灣科技大學 |
|
11:15 |
D3-6 |
A Wide-Range Synchronous 50% Duty-Cycle Clock Generator |
| |
PDF |
Wei-Hao Chiu and Tsung-Hsien Lin, 國立台灣大學 |