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13:30 |
E1-1 |
Topology Generation and Floorplanning for Low Power Application-Specific
Network-on-Chips |
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PDF |
Wan-Yu Lee and Iris Hui-Ru Jiang, 國立交通大學 |
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13:45 |
E1-2 |
SAT Based Boolean Matching with Don't Cares |
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PDF |
Kuo-Hua Wang and Chung-Ming Chan, 輔仁大學 |
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14:00 |
E1-3 |
Lithography-Aware Routing with Predictive OPC Formulae |
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PDF |
Tai-Chen Chen, Guang-Wan Liao, and Yao-Wen Chang, 國立台灣大學 |
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14:15 |
E1-4 |
An Efficient Energy Modeling Approach for VLIW DSP at Instruction-Level |
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PDF |
Wen-Tsan Hsieh, Hsin-Ying Liao, Chien-Nan Jimmy Liu, Shu-Yu Cheng, and Ji-Jan
Chen, 國立中央大學 |
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14:30 |
E1-5 |
An Automated Synthesis Tool for Fully Differential OPAMPs |
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PDF |
Cheng-Wu Lin and Soon-Jyh Chang, 國立成功大學 |
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14:45 |
E1-6 |
A Top-down, Mixed-level Design Methodology for CT BP ΔΣ Modulator Using
Verilog-A |
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PDF |
Hung-Yuan Chu and Chien-Hung Tsai, 國立成功大學 |