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10:00 |
E2-1 |
Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode
Segmented Scan Architecture |
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PDF |
Sying-Jyan Wang, Po-Chang Tsai, Hung-Ming Weng, and Katherine Shu-Min Li,
國立中興大學 |
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10:15 |
E2-2 |
Test Efficiency Analysis of SOC Test Platforms |
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PDF |
Tong-Yu Hsieh, Kuen-Jong Lee, and Jian-Jhih You, 國立成功大學 |
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10:30 |
E2-3 |
A Novel High-Speed SOC Test Scheme Using Virtual TAMs |
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PDF |
Jiann-Chyi Rau, Chien-Hsu Wu, and Chung-Lin Wu, 淡江大學 |
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10:45 |
E2-4 |
Enhancing Compression Efficiency with Skewed-Probability Scan Chains |
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PDF |
Sying-Jyan Wang, Shih-Cheng Chen, and Katherine Shu-Min Li, 國立中興大學 |
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11:00 |
E2-5 |
DIAGNOSIS OF MULTIPLE SCAN CHAIN TIMING FAULTS |
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PDF |
Wei-Shun Chuang, Wei-Chih Liu, and James Chien-Mo Li, 國立台灣大學 |
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11:15 |
E2-6 |
Testing MRAM for Write Disturbance Fault |
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PDF |
Wan-Yu Lo, Ching-Yi Chen, Chin-Lung Su, and Cheng-Wen Wu, 國立清華大學 |