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10:00 |
E3-1 |
Throughput-Aware Floorplanning by Considering Multiple Critical Cycles |
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PDF |
Li-Ya Wang and Juinn-Dar Huang, 國立交通大學 |
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10:15 |
E3-2 |
SIMD Code Generation for Multimedia |
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PDF |
Cheng-Cho Jean, Guang-Huei Lin, Sao-Jie Chen, and Alan P. Su, 國立台灣大學
|
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10:30 |
E3-3 |
H.264 Decoder Optimization – VLIW DSP Platform |
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PDF |
Pou-Hang Ian, Jia-Ming Chen, Hsin-Wen Wei, Jian-Liang Luo, and Wei-Kuan
Shih, 國立清華大學 |
|
10:45 |
E3-4 |
H.264/AVC Baseline Profile Decoder Optimization on PAC DSP |
| |
PDF |
Chiu-Ling Chen, Jia-Ming Chen, Jian-Liang Luo, Tien-Wei Hsieh, and
Wei-Kuan Shih, 國立清華大學 |
|
11:00 |
E3-5 |
SIMD Optimizations for PAC VLIW DSP Processors with Sub-word
Instructions |
| |
PDF |
Ci-Bang Kuan and Jenq Kuen Lee, 國立清華大學 |
|
11:15 |
E3-6 |
Standard Cell Like Via-Configurable Logic Block Design for Structured
ASICs |
| |
PDF |
Mei-Chen Li, Chien-chung Lai, Hui-Hsiang Tung, and Rung-Bin Lin, 元智大學 |