TECHNICAL PROGRAM
Session
P1A |
Day
08/08
|
Time
13:30-16:00
|
Chair
李博明 教授
南台科技大學 |
Room
2F宴會廳 |
P1A-1 |
Frequency Domain Analog Circuit Fault Diagnosis Based on Radial Basis
Function Neural Network |
PDF |
林宗志、郭明仁、陳盈州, 逢甲大學 |
P1A-2 |
A RF CMOS Low Noise Amplifier Using High-Q Active Inductor Loads with
Binary Code for Multi-Band Applications |
PDF |
Jenn-Tzer Yang, Yuan-Hao Lee, Yi-Yuan Huang, Yu-Min Mu, and Yen-Ching
Ho, 明新科技大學 |
P1A-3 |
A Novel Precise Step-Shaped Soft-Start Technique for Integrated DC-DC
Converter |
PDF |
Yung-Chun Chuang and Ke-Horng Chen, 國立交通大學 |
P1A-4 |
A self-oscillating switching power amplifier |
PDF |
Chia-Hsiung Kao, Ping-Yu Tsai, Wen-Pin Lin, and Ming-Ching Chou, 國立中山大學 |
P1A-5 |
Differential Feed-forward Transconductor Design for High Linearity WiMax
Subharmonic Mixer |
PDF |
Ying-Ta Lu, Hsien-Yuan Liao, Shao-Liang Lu, Joseph D. S. Deng*, and
Hwann-Kaeo Chiou, 國立中央大學 |
P1A-6 |
Modeling on the Mutual Inductance of On-Chip Transformers |
PDF |
Heng-Ming Hsu, Sih-Han Lai, and Hsien-Feng Liao, 國立中興大學 |
P1A-7 |
A 1.76 uW, 0.9V, 8-bit Successive Approximation Register ADC with
Fully-Differential Input Capability |
PDF |
謝宗殷、洪浩喬, 國立交通大學 |
P1A-8 |
A 3.1–10.6 GHz Ultra-Wideband CMOS Low Noise Amplifier Using
Bridged-Shunt-Series Peaking Technique |
PDF |
Yu-Liang Lin, Feng-Lin Shiu, and Hwann-Kaeo Chiou, 國立中央大學 |
P1A-9 |
A Novel Infrared Tracking System with Winner-Take-All Implementation |
PDF |
Po-Hsiang Chang and Chih-Hsiung Shen, 國立彰化師範大學 |
P1A-10 |
A New Multi-Function Wave Generator Based on Multiple-Output
Second-Generation Current Conveyors |
PDF |
Yuh-Shyan Hwang, Yu-Wen Chen, Jiann-Jong Chen, and Wen-Ta Lee, 國立台北科技大學 |
P1A-11 |
Design a Multiplicative type-II Fuzzy Cellular Neural Network with CMOS
Image Sensor |
PDF |
Jui-Lin Lai, Yuan-Hung Lo, Yan-Ting Chen, and Rong-Jian Chen, 國立聯合大學 |
P1A-12 |
A 2.4GHz Current-reused VCO with Degenerated Resistors |
PDF |
Ruey-Lue Wang, Guo-Ruey Tsai , Yu-Feng Lin, and YuJo Tzeng, 崑山科技大學 |
|
TECHNICAL PROGRAM
Session
P1E |
Day
08/08
|
Time
13:30-16:00
|
Chair
黃宗柱 教授
國立彰化師範大學 |
Room
2F宴會廳 |
P1E-1 |
A Single-Clock Enhanced Random Access Scan |
PDF |
Chen-An Chen, Wei-Yi He, and Tsung-Chu Huang, 國立彰化師範大學 |
P1E-2 |
Area-Driven Decoupling Capacitance Allocation Based on Space Sensitivity
Analysis |
PDF |
Jin-Tai Yan, Ming-Yuen Wu, and Zhi-Wei Chen, 中華大學 |
P1E-3 |
A Topology-Based Construction for X-Architecture Clock Routing |
PDF |
Chia-Chun Tsai*, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, and
Rong-Shue Hsiao, 南華大學 |
P1E-4 |
Routability-Driven Track Routing for Coupling Capacitance Reduction |
PDF |
Jin-Tai Yan, Zhi-Wei Chen, and Kuen-Ming Lin, 中華大學 |
P1E-5 |
A Timing-Driven X-Architecture Router with Obstacles |
PDF |
Shu-Ping Chang, Hsin Hsiung Huang, Yu-Cheng Lin, and Tsai Ming Hsieh,
國立台東大學 |
P1E-6 |
Test Generation for Transition Delay and RS-CFM Faults in Modified Booth
Multipliers |
PDF |
Hsing-Chung Liang and Pao-Hsin Huang, 中原大學 |
P1E-7 |
Non-Slicing Floorplanning-Based Crosstalk Reduction on Gridless Track
Assignment |
PDF |
Win-Nai Zheng, Yu-Ning Zhang, and Yih-Lang Li, 國立交通大學 |
P1E-8 |
Modified Essential Spare Pivoting Algorithm for Embedded Memories with
Global Block-Based Redundancy |
PDF |
Chun-Lin Yang and Shyue-Kung Lu, 輔仁大學 |
|
TECHNICAL PROGRAM
Session
P1D |
Day
08/08
|
Time
13:30-16:00
|
Chair
莊作彬 教授
國立屏東商業技術學院 |
Room
2F宴會廳 |
P1D-1 |
A Comparative Study of LNS and Floating-Point arithmetic |
PDF |
Chih-Yen Fan and Chi-Chyang Chen, 逢甲大學 |
P1D-2 |
Design of Low-Error Signed Fixed-Width Multipliers |
PDF |
Jiun-Ping Wang and Shiann-Rong Kuang, 國立中山大學 |
P1D-3 |
A Novel VLSI Iterative Division Algorithm for Fast Quotient Generation |
PDF |
Tso-Bing Juang, 國立屏東商業技術學院 |
P1D-4 |
Reusing Cache for Real-Time Memory Address Trace Compression |
PDF |
Chung-Fu Kao, Chun-Hung Lai, and Ing-Jer Huang, 國立中山大學 |
P1D-5 |
A Novel Membership Function Approximation for Effective Digital Circuit
Design of Neural Networks |
PDF |
Che-Wei Lin and Jeen-Shing Wang, 國立成功大學 |
P1D-6 |
A Novel Architecture for Self-Reconfigurable Systems |
PDF |
Trong-Yen Lee, Yung-Lin Hsu, and Che-Cheng Hu, 國立台北科技大學 |
P1D-7 |
VLSI Implementation for Block-Based Gradient Domain High Dynamic Range
Compression |
PDF |
Tsun Hsien Wang, Wei-Ming Ke, Chih-Hsueh Huang, Ding-Chuang Zwao, Fang-Chu
Chen, and Ching-Te Chiu, 國立清華大學 |
P1D-8 |
High Performance Decoder Design for Convolutional LDPC Codes |
PDF |
Mu-Chung Chen, Jun-Wei Lin, Yen-Shuo Chang, Jin-Hao Yu, and Tzi-Dar
Chiueh, 國立台灣大學 |
P1D-9 |
A Novel Design for Computation of All Transforms in H.264/AVC Decoders |
PDF |
Yi-Chih Chao, Hui-Hsien Tsai, Yu-Hsiu Lin, Jar-Ferr Yang, and Bin-Da
Liu, 國立成功大學 |
P1D-10 |
Design of a 2X2 MIMO OFDM Transceiver With Correction of Different
Carrier Frequency Offsets at Transmitter Antennas |
PDF |
Li-Wen Hsu and Dah-Chung Chang, 國立中央大學 |
|