Analog

P2A-1	A 5-bit 1 GSample/s Two-Stage ADC with a New Flash Folded Architecture
PDF	Hung-Yu Huang, Ying-Zu Lin, and Soon-Jyh Chang, 國立成功大學
P2A-2	A CMOS Temperature Sensor Design for Implantable Bio-Medical Devices
PDF	Ying-Hsiang Wang, Wen-Yaw Chung, Chiung-Cheng Chuang, and Chien-Hsi Kao, 中原大學
P2A-3	Low Dropout Voltage Regulator with Current-Limit Circuit
PDF	Chien-Cheng Chen, Nan-Xiong Huang, Miin-Shyue Shiau, Hong-Chong Wu, and Don-Gey Liu, 逢甲大學
P2A-4	Novel Devices Merging RITD and CMOS for Future VLSI Use
PDF	Jyi-Tsong Lin, Wei-Chin Lin, and Chao-Yu Hou, 國立中山大學
P2A-5	Using Output-Clamped Amplifier to Implement Time-Based Interface Circuit for Measuring Tiny Grounded Capacitance
PDF	Wei-Hung Hsu and Meng-Lieh Sheu, 國立暨南國際大學
P2A-6	A Low Distortion Class-AB Power Amplifier With Active Tuning
PDF	Ro-Min Weng, Chi-Wen Tsai, and Kuen-Yi Lin, 國立東華大學
P2A-7	A Low Power 1V 10-bit Successive Approximation ADC
PDF	Yi-Hung Chen, Wan-Tin Lin, and Hwang-Cherng Chow, 長庚大學
P2A-8	New Low Supply-Bounce Current-Mode Shunt Regulator
PDF	Che-Min Kung, Chan-Min Pan, Jiann-Jong Chen, Yuh-Shyan Hwang, and Wen-Ta Lee, 國立台北科技大學
P2A-9	CMOS BANDGAP REFERENCE WITH CURVATURE COMPENSATION ON HIGHER ORDER TEMPERATURE TERMS
PDF	Hong-Yi Huang and Ru-Jie Wang, 國立台北大學
P2A-10	A Temperature-Compensation CMOS Subbandgap Reference with 1V Power Supply Operation
PDF	Hung-Wei Chen, Jing-Yu Luo, and Wen-Cheng Yen, 國立聯合大學
P2A-11	6 Gb/s Digitally Phase Adjusted Clock Data Recovery for Spread Spectrum Clock
PDF	Chin-Hsien Lin, Yuan-Pu Cheng, Yen-Ying Huang, and Shyh-Jye Jou, 國立交通大學

　

EDA

P2E-1	Don't-Care Bits Filling for Reducing Capture Power
PDF	Wang-Dauh Tseng, Lung-Jen Lee, and Chun-Kai Hsu, 元智大學
P2E-2	Mismatch Address Index Encoding for Data Compression in Scan Test
PDF	Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, and Hcc-Hang Jang, 元智大學
P2E-3	Reduction of Power Dissipation during Scan Testing by Test Vector Ordering
PDF	Wang-Dauh Tseng and Lung-Jen Lee, 元智大學
P2E-4	A Simulation-based Redundancy Identification in Combinational Circuits
PDF	Yi-Yuan Huang and Chun-Yao Wang, 國立清華大學
P2E-5	An Experimentation Suite for Education in Low-Noise Design
PDF	You-wei Liang, Shinyu Chen, and Robert Rieger, 國立中山大學
P2E-6	Performance Improvement using Application-Specific Instructions under Hardware Constrains
PDF	Chijie Lin, Jiying Wu, Jerung Shiu, Desheng Chen, and Yiwen Wang, 逢甲大學
P2E-7	Power-Aware Memory Mapping for FPGAs
PDF	Tien-Yuan Hsu, Ting-Chi Wang, and Kuang-yao Lee, 國立清華大學
P2E-8	MFASE Multiple Functions SoCs Analysis Environment
PDF	Ya-Shu Chen, Shih-Chun Chou, Chi-Sheng Shih, and Tei-Wei Kuo, 國立台灣大學

　

Digital

P2D-1	An Integrated Spatial-Temporal Sampling Rate Conversion Architecture by Motion Compensation for TV Display
PDF	Chih-Hung Kuo, Li-Chuan Chang, Zheng-Wei Liu, and Bin-Da Liu, 國立成功大學
P2D-2	A Novel Look-up Table-Based Multiplication/Squaring Architecture for Cryptosystems over GF(2sup/m/)
PDF	Wen-Ching Lin, Jun-Hong Chen, and Ming-Der Shieh, 國立成功大學
P2D-3	A DPA-Resistant AES Encryption Hardware Module
PDF	Kuan Jen Lin, Shih Hsien Yang, and Chih Hsuan Hsu, 輔仁大學
P2D-4	A Low-Hardware-Cost Logical OR Operation Log-SPA LDPC Decoder
PDF	Ming-Yu Lin, Ching-Da Chan, Jung-Chieh Chen, and Po-Hui Yang, 國立雲林科技大學
P2D-5	Mixed-Vth (MVT) CMOS Circuit Design For Low Power Cell Libraries
PDF	Jyun-Yi Lin, Li-Rong Wang, Chia-Lin Hu, and Shyh-Jye Jou, 國立交通大學
P2D-6	Symbol and Integer Carrier Frequency Offset Synchronization for IEEE802.16e
PDF	Juan-Nan Lin, Hsiao-Yun Chen, and Shyh-Jye Jou, 國立交通大學
P2D-7	Register Processor for MMX instructions
PDF	Jih-Ching Chiu, Shou-Xi Hong, and Kai-Ming Yang, 國立中山大學
P2D-8	Performance Comparisons and Tradeoffs of Table-Based Arithmetic Function Evaluators
PDF	Ping-Chung Wei, Ching-Pin Lin, and Shen-Fu Hsiao, 國立中山大學
P2D-9	Multiple-Input XOR/XNOR Circuit Design Using Pass-Transistor Logic and Its Application in Cryptography
PDF	Ming-Yu Tsai, Chia-Sheng Wen, and Shen-Fu Hsiao, 國立中山大學
P2D-10	Efficient Design of Graphic Rasterization Module
PDF	Chung-Hua Tsai and Yun-Nan Chang, 國立中山大學