Tutorial (1)

主講人介紹：

Ming-Dou Ker received the B.S. degree from the Department of Electronics Engineering and the M.S. and Ph.D. degrees from the Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 1986, 1988, and 1993, respectively.

He was ever worked as the Department Manager in the VLSI Design Division of the Computer and Communication Research Laboratories (CCL), Industrial Technology Research Institute (ITRI), Taiwan. Now, he has been a Full Professor in the Department of Electronics Engineering, National Chiao-Tung University, Taiwan. Currently, he also serves as the Director of Master Degree Program in the College of Electrical Engineering and Computer Science, National Chiao-Tung University; as well as the Associate Executive Director of National Science and Technology Program on System-on-Chip, Taiwan. In the field of reliability and quality design for circuits and systems in CMOS technology, he has published over 290 technical papers in international journals and conferences. He has proposed many inventions to improve reliability and quality of integrated circuits, which have granted with 120 U.S. patents and 132 ROC (Taiwan) patents. His current research topics include reliability and quality design for nanoelectronics and gigascale systems, high-speed and mixed-voltage I/O interface circuits, and on-glass circuits for system-on-panel applications in TFT LCD display. Prof. Ker had been invited to teach or to consult reliability and quality design for integrated circuits by hundreds of design houses and semiconductor companies in the worldwide IC Industry.

Dr. Ker has served as member of the Technical Program Committee and Session Chair of numerous international conferences. He is the Organizer of the Special Session on ESD Protection Design for Nanoelectronics and Gigascale Systems in ISCAS 2005. He taught the Tutorial Course on the topic of ESD (Electrostatic Discharge) Protection Design for Nanoelectronics in CMOS Technology in ISCAS 2006. He was selected as the Distinguished Lecturer in IEEE Circuits and Systems Society for year 2006-2007. He also served as Associate Editor of IEEE Trans. on VLSI Systems. He was the President of Foundation in Taiwan ESD Association. In 2003, he was selected as one of the Ten Outstanding Young Persons in Taiwan by Junior Chamber International (JCI). In 2005, one of his patents on ESD protection design has been awarded with the National Invention Award in Taiwan.

內容摘要：

I/O cells are one of basic building blocks in CMOS integrated circuits. Typically, in digital applications, there are input cells, output cells, input/output (I/O) cells, I/O power (VDD/VSS) cells, core power (VDD/VSS) cells, and corner cells. In analog applications, there will be analog I/O cell, analog power (VDD/VSS) cells, and power-cut cells. Especially, in some high-speed I/O interface, such as HDMI or PCI express, the low-capacitance I/O cell is strongly requested by IC Industry. The basic function and driving current of I/O circuit can be calculated by HSPICE simulation to fine tune the device dimensions of pull-up/ pull-down transistors in the I/O cells. Currently, the transistor has been scaled toward the nanometer region and the power supply voltage of chips in the nanoscale CMOS technology has been also decreased due to the reliability and power consumption issues. Obviously, the shrunk device dimension makes the chip area smaller to save silicon cost. The lower power supply voltage (VDD) results in lower power consumption. Therefore, chip design quickly migrates toward the lower voltage level with the advancements of the nanoscale CMOS technology. However, some peripheral components or other ICs in a microelectronic system could be still operated at a higher voltage levels, such as 3.3 V or 5 V. Thus, the I/O circuits must be designed in low-voltage CMOS process, but to be operated in a high-voltage or mixed-voltage (high-voltage and low-voltage) environment. The I/O circuits operated in the high-voltage or mixed-voltage environment often suffer the issues of gate-oxide reliability, hot-carrier degradation, and leakage current path.

In this tutorial, the design of I/O cells for mixed-voltage I/O interface realized in low-voltage CMOS processes without gate-oxide reliability issue will be presented. Several new circuit skills will be shown how to use the low-voltage devices to realize the I/O cells for applications in mixed-voltage environments. Besides the gate-oxide reliability of I/O cells in mixed-voltage I/O interface, I/O cells are often requested to sustain high enough robustness against electrostatic discharge (ESD) stresses. Typically, for safe production of ICs, the ESD robustness for commercial IC products has been requested to sustain ESD levels of ±2kV in the HBM (Human Body Model) ESD test, ±200V in the MM (Machine Model) ESD test, and ±1kV in the CDM (Charged Device Model) ESD test. I/O cells should be designed with on-chip ESD protection devices or circuits to achieve the requested ESD levels. In this tutorial, basic ESD protection concept will be included, and some process-related solutions with additional mask layers provided by Foundry will be also introduced. The process-portable ESD protection solution for I/O cells by circuit skill will be emphasized. The active power-rail ESD clamp circuit has been found to be a key role in IC products to provide high ESD robustness. The design on power (VDD/VSS) cells with active power-rail ESD clamp circuit will be presented. Finally, the layout example of I/O cells in 90-nm and 130-nm CMOS processes will be shown.