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Paper
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Authors and Contact Affiliation |
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1 |
PDF |
6 Gb/s Digitally Phase Adjusted Clock Data Recovery for Spread Spectrum Clock
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Chin-Hsien Lin, Yuan-Pu Cheng, Yen-Ying Huang and Shyh-Jye Jou,
國立交通大學 |
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2 |
PDF |
80-S/s Delta Sigma Modulators For IR Thermometer
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Jen-Shiun Chiang, Hsin-Liang Chen, Yao-Tsung Chang, and Meng-Hsuan Ho, 淡江大學
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3 |
PDF |
A 0.8V SOP-Based Wideband Fourth-Order Cascade Delta-Sigma Modulator
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Chien-Hung Kuo, and Shuo-Chau Chen, 淡江大學
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4 |
PDF |
A 1.76 uW, 0.9V, 8-bit Successive Approximation Register ADC with Fully-Differential Input Capability
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謝宗殷 洪浩喬, 國立交通大學 |
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5 |
PDF |
A 14-Bit Fourth-Order Sigma-Delta Modulator with Feedforward Architecture for Hearing Aid
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Shuenn-Yuh Lee, Jia-Hua Hong, Chi-Ching Lin, Chui-Kum Chiu, and Sheng-Jing Ku, 國立中正大學
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6 |
PDF |
A 1-V CMOS Pseudo-Differential Amplifier
with Multiple Common Mode Stabilization
and Frequency Compensation Loops |
Meng-Hung Shen, Po-Hsiang Lan and Po-Chiun Huang, 國立清華大學
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7 |
PDF |
A 1-V Fully Differential Amplifier with
Buffered Nested-Miller Compensation |
Li-Wen Wang, Meng-Hung Shen and Po-Chiun Huang, 國立清華大學
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8 |
PDF |
A 2.4GHz Current-reused VCO with Degenerated Resistors
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Ruey-Lue Wang, Guo-Ruey Tsai , Yu-Feng Lin, YuJo Tzeng, 崑山科技大學
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9 |
PDF |
A 2.5 Gbps CMOS Fully Integrated Optical Receicer with Lateral PIN Detector |
Wei-Zen Chen and Shih-Hao Huang, 國立交通大學
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10 |
PDF |
A 3.1–10.6 GHz Ultra-Wideband CMOS Low Noise Amplifier Using Bridged-Shunt-Series Peaking Technique
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Yu-Liang Lin, Feng-Lin Shiu, and Hwann-Kaeo Chiou,
國立中央大學 |
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11 |
PDF |
A 5-bit 1 GSample/s Two-Stage ADC with a New Flash Folded Architecture
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Hung-Yu Huang, Ying-Zu Lin and Soon-Jyh Chang, 國立成功大學
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12 |
PDF |
A 8-BIT 150-MS/S FULLY DIFFERENTIAL DUAL-CHANNEL TIME-INTERLEAVED PIPELINE A/D CONVERTER
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Chih-Hsiang Chang and Ching-Yuan Yang, 國立中興大學
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13 |
PDF |
A CMOS Low-Noise Amplifier with Shunt-Peaking for 3-5GHz Ultra-Wideband Wireless System
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Zhe-Yang Huang, Che-Cheng Huang, and Chung-Chih
Hung, 國立交通大學 |
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14 |
PDF |
A CMOS Temperature Sensor Design for Implantable Bio-Medical Devices
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Ying-Hsiang Wang, Wen-Yaw Chung, Chiung-Cheng Chuang, Chien-Hsi Kao, 中原大學
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15 |
PDF |
A CMOS-MEMS Frequency Adaptive Resonator with Multiple Electrostatic Electrodes Driving.
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J. C. Chiou and L. J. Shieh, 國立交通大學 |
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16 |
PDF |
A compact square-root domain filter |
Chia-Hsiung Kao, Ping-Yu Tsai, Wen-Pin Lin and Wan Chen Lo, 國立中山大學
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17 |
PDF |
A Comparative Study of LNS and Floating-Point arithmetic
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Chih-Yen Fan and Chi-Chyang Chen, 逢甲大學
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18 |
PDF |
A Conditional Isolation Technique for Low-Power and High-speed Wide Domino Gates
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Wei-Hao Chiu and How-Rern Lin, 大葉大學 |
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19 |
PDF |
A Design Methodology for Application-Specific Instruction-set Processors with Memory Access Considerations
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Ji-Ying Wu, Chi-Jie Lin, Je-Rung Shiu, De-Sheng Chen, Yi-Wen Wang, 逢甲大學
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20 |
PDF |
A DPA-Resistant AES Encryption Hardware Module
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Kuan Jen Lin, Shih Hsien Yang and Chih
Hsuan Hsu, 輔仁大學
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21 |
PDF |
A Dual Phase Charge Pump with Compact Size
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Po-Chin Fan and Ke-Horng Chen, 國立交通大學
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22 |
PDF |
A Dual-Mode Step-Up DC/DC Converter with Current-Limiting Technology
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Chun-Ting Kuo, Wan-Rone Liou and Ping-Hsing Chen, 國立台灣海洋大學
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23 |
PDF |
A Energy-Efficient 256X144 TCAM Design
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Wen-Yen Liu, Po-Tsang Huang, and Wei Hwang, 國立交通大學
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24 |
PDF |
A Flip-Flop Replacement Technique for IR Drop Reduction
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Jiun-Kuan Wu, Liang-Ying Lu, Kuang-Yao Chen,Tsung-Yi Wu, 國立彰化師範大學
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25 |
PDF |
A HIGH PERFORMANCE CAVLC DECODER USING NON-ZERO SKIP AND MULTI-LEVEL DECODING
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Tsung-Han Tsai and De-Lung Fang, 國立中央大學
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26 |
PDF |
A High-Resolution All-Digital Phase-Locked Loop with its Application to Built-In Speed Grading for Memory
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Hsuan-Jung Hsu, Chun-Chieh Tu, and Shi-Yu Huang , 國立清華大學
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27 |
PDF |
A HQPM-Based Transmitter with Digital Predistortion Scheme for Enhancing Average Efficiency
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C.-T. Chen, C.-J. Li, T.-S. Horng,
J.-K. Jau,
J.-Y. Li, P.-K. Horng, D.-S. Deng, 國立中山大學 |
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28 |
PDF |
A Low Distortion Class-AB Power Amplifier With Active Tuning
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Ro-Min Weng, Chi-Wen Tsai, and Kuen-Yi
Lin, 國立東華大學 |
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29 |
PDF |
A Low Jitter 2.5-GHz Self-Calibration PLL
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鄭國興、蔡玉章、洪凱尉, 國立中央大學 |
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30 |
PDF |
A Low Power 1V 10-bit Successive Approximation ADC
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Yi-Hung Chen, Wan-Tin Lin and Hwang-Cherng Chow, 長庚大學
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31 |
PDF |
A Low Power Tree-Type Multiplexer with Embedded Timing Skew Switch
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HungWen Lu, 國立中央大學 |
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32 |
PDF |
A Low Power Wide Range Duty Cycle Corrector Based on Pulse Shrinking/Stretching Mechanism
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Poki Chen, Shi-Wei Chen, Juan-Shan Lai, 國立台灣科技大學
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33 |
PDF |
A Low Voltage Full-band Cascoded UWB LNA
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Ruey-Lue Wang, Min-Chhuien Lin, Zhi-Cheng Lin, 崑山科技大學
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34 |
PDF |
A Low-Complex Image Coding Algorithm Based on Wavelet Transform
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Trong-Yen Lee, Yang-Hsin Fan and Su-Zhen Hong, 國立台北科技大學
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35 |
PDF |
A Low-Complexity High-Performance Two-Dimensional
Look-Up Table for LDPC Hardware Implementation |
Tzu-Wen Chung, Chen-Pang Chang, Jung-Chieh Chen, Po-Hui Yang, 國立高雄師範大學
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36 |
PDF |
A Low-Hardware-Cost Logical OR Operation Log-SPA LDPC Decoder
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Ming-Yu Lin, Ching-Da Chan, Jung-Chieh Chen, Po-Hui Yang, 國立雲林科技大學
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37 |
PDF |
A Low-jitter Phase-rotation Spread Spectrum Clock Generator
for Serial ATA 6Gbps Clock and Data Recovery
|
Chi- Hsien Lin, Yen-Ying Huang, Shu-Rung Li, Yuan-Pu Cheng and Shyh- Jye Jou,
國立交通大學 |
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38 |
PDF |
A Low-Power High-Gain Rail-to-Rail Input/Output Operational Amplifier
|
Chien-Hung Kuo, Hwa-Ming Lu, and Wei-Hsien Fang, 淡江大學
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39 |
PDF |
A Mini Stereo Digital Audio Processor Design
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Po-Yu Kuo, Dian Zhou, Zhi-Ming Lin,, 德州大學達拉斯分校
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40 |
PDF |
A Multi-Code Rate IEEE 802.16e LDPC Decoder Design
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Chih-Hao Hsiao and Yun-Nan Chang, 國立中山大學
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41 |
PDF |
A Network-Flow Based Algorithm for Digital Microfluidic Biochip Routing
|
Ping-Hung Yuh, Chia-Lin Yang, and Yao-Wen
Chang, 國立台灣大學 |
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42 |
PDF |
A New Current-Mode Wheatstone Bridge Based on Fully Differential Operational Transresistance Amplifiers
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Yuh-Shyan Hwang, Chun-Chi Shih, Jiann-Jong Chen, Wen-Ta Lee, 國立台北科技大學
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43 |
PDF |
A New Multi-Function Wave Generator Based on Multiple-Output Second-Generation Current Conveyors
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Yuh-Shyan Hwang, Yu-Wen Chen, Jiann-Jong Chen, Wen-Ta Lee, 國立台北科技大學
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44 |
PDF |
A New Self-Oscillating CMOS DC-DC Converter with Adaptive Mode-Switching Mechanism
|
Sau-Mou Wu , Chung-Lin Wu and Chia-Hsien Chang, 元智大學
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45 |
PDF |
A Novel Architecture for Self-Reconfigurable Systems
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Trong-Yen Lee, Yung-Lin Hsu, Che-Cheng Hu, 國立台北科技大學
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46 |
PDF |
A Novel CMOS Smart Temperature Sensor for On-Line Thermal Monitoring
|
Wei-Cheng Lee, Hung-Chih Lin, and Tsin-Yuan
Chang, 國立清華大學 |
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47 |
PDF |
A Novel Design for Computation of All Transforms in H.264/AVC Decoders
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Yi-Chih Chao, Hui-Hsien Tsai, Yu-Hsiu Lin, Jar-Ferr Yang, and Bin-Da Liu, 國立成功大學
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48 |
PDF |
A Novel High-Speed SOC Test Scheme Using Virtual TAMs
|
Jiann-Chyi Rau, Chien-Hsu Wu, Chung-Lin Wu, 淡江大學
|
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49 |
PDF |
A Novel Infrared Tracking System with Winner-Take-All Implementation
|
Po-Hsiang Chang, Chih-Hsiung Shen,
國立彰化師範大學 |
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50 |
PDF |
A Novel Log-Lin-Log Response CMOS Image Sensor with High Swing and Wide Dynamic Range
|
Sau-Mou Wu and Ming-Wei Chen, 元智大學
|
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51 |
PDF |
A Novel Look-up Table-Based Multiplication/Squaring Architecture for Cryptosystems over GF(2sup/m/)
|
Wen-Ching Lin, Jun-Hong Chen, and Ming-Der Shieh,
國立成功大學 |
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52 |
PDF |
A Novel Low Complexity Pulse-Triggered Flip-Flop Design with Dual Triggering Mode
|
Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu and Wei-Rong Ciou, 國立中興大學
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53 |
PDF |
A Novel Membership Function Approximation for Effective Digital Circuit Design of Neural Networks
|
Che-Wei Lin and Jeen-Shing Wang, 國立成功大學
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54 |
PDF |
A Novel Precise Step-Shaped Soft-Start Technique for Integrated DC-DC Converter
|
Yung-Chun Chuang and Ke-Horng Chen, 國立交通大學 |
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55 |
PDF |
A Novel VLSI Iterative Division Algorithm for Fast Quotient Generation
|
Tso-Bing Juang, 國立屏東商業技術學院 |
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56 |
PDF |
A Partially Parallel Low-Density Parity Check Code Decoder with Reduced Memory for Long Code-Length
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Chin-Kuang Lian, Shin-Yo Lin, Tsung-Han Tsai, Chin-Long Wey, 國立中央大學
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57 |
PDF |
A Protocol-Reconfigurable Double-Layer External Memory Management for H.264/AVC Decoder
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Chang-Hsuan Chang, Ming-Hung Chang, and Wei Hwang, 國立交通大學
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58 |
PDF |
A Quarter-Rate 2.56/3.2Gbps 16/20:1 SERDES Interface in 0.18μm CMOS technology
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Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, YarSun Hsu, Ming-Hao Lu, Ping-Lin Yang, Fan-Ta Chen, You-Hung Li, Yu-Hao Hsu, Min-Sheng
Kao, 國立清華大學 |
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59 |
PDF |
A Redundancy Detection Algorithm for DCT and Quantization in H.264 Video Encoding
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Ting-Wei Chen, Chang-Hsin Cheng, Yu Liu, Chun-Lung Hsu, 國立東華大學
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60 |
PDF |
A RF CMOS Low Noise Amplifier Using High-Q Active Inductor Loads with Binary Code for Multi-Band Applications
|
Jenn-Tzer Yang, Yuan-Hao Lee, Yi-Yuan Huang, Yu-Min Mu, and Yen-Ching Ho, 明新科技大學
|
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61 |
PDF |
A SAR-Based Smart Temperature Sensor with Binary-Weighted Search Algorithm
|
Chun-Chi Chen, Poki Chen, and Kai-Ming Wang, 國立台灣科技大學
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62 |
PDF |
A Scalable Frame-Pipeline Motion Estimation Processor for Full-Search Algorithm
|
Yeong-Kang Lai, Lien-Fei Chen, Yin-Ruey Huang, and Sheng-Yu Huang, 國立中興大學
|
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63 |
PDF |
A Scalable Graph-cut Engine Architecture for Real-time Vision
|
Nelson Yen-Chung Chang, Tian-Sheuan Chang,
國立交通大學 |
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64 |
PDF |
A Scalable Wavelet Image Coder Based on Zero-block and Array and Its Hardware Implementation
|
Yuan-Long Jeang, Hung-Yu Wang, Cyuan-Cheng Wong, 崑山科技大學
|
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65 |
PDF |
A self-oscillating switching power amplifier
|
Chia-Hsiung Kao, Ping-Yu Tsai, Wen-Pin Lin and Ming-Ching Chou, 國立中山大學
|
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66 |
PDF |
A Simple Yet Efficient Global Router with Mirrored Monotonic Routing and Reduced Multi-Source Multi-Sink Maze Routing
|
Ke-Ren Dai, Jyun-Yi Lin, and Yih-Lang Li,
國立交通大學 |
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67 |
PDF |
A Simulation-based Redundancy Identification in Combinational Circuits
|
Yi-Yuan Huang, Chun-Yao Wang, 國立清華大學
|
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68 |
PDF |
A Single-Clock Enhanced Random Access Scan
|
Chen-An Chen, Wei-Yi He and Tsung-Chu
Huang, 國立彰化師範大學 |
|
69 |
PDF |
A Temperature-Compensation CMOS Subbandgap Reference with 1V Power Supply Operation
|
Hung-Wei Chen, Jing-Yu Luo, Wen-Cheng Yen, 國立聯合大學
|
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70 |
PDF |
A Timing-Driven X-Architecture Router with Obstacles
|
Shu-Ping Chang, Hsin Hsiung Huang, Yu-Cheng Lin, and Tsai Ming Hsieh,
國立台東大學 |
|
71 |
PDF |
A Top-down, Mixed-level Design Methodology for CT BP ΔΣ Modulator Using Verilog-A
|
Hung-Yuan Chu, Chien-Hung Tsai, 國立成功大學
|
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72 |
PDF |
A Topology-Based Construction for X-Architecture Clock Routing
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Chia-Chun Tsai*, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, and Rong-Shue Hsiao, 南華大學
|
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73 |
PDF |
A Transitive-Closure-Graph-Based Macro Placement Algorithm
|
Hsin-Chen Chen, Yi-Lin Chuang, Zhe-Wei Jiang, and Yao-Wen Chang, 國立台灣大學
|
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74 |
PDF |
A UWB CMOS Power Amplifier With Differential to Single-Ended Converter
|
Shuenn-Yuh Lee and Guan-Da Lu, 國立中正大學
|
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75 |
PDF |
A Wide-Band Low-Power Quadrature VCO
|
Ching-Yi Chen, 國立中正大學 |
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76 |
PDF |
A Wide-Range Synchronous 50% Duty-Cycle Clock Generator
|
Wei-Hao Chiu and Tsung-Hsien Lin, 國立台灣大學
|
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77 |
PDF |
Adaptive Sensing Control in SRAM Design Using Per-Column Timing Tracking Scheme
|
Ya-Chun Lai, Ming-Yi Chang, and Shi-Yu Huang, 國立清華大學
|
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78 |
PDF |
All-Digital PLL Using Bulk-Controlled Varactor and Pulse-Based DCO
|
Hong-Yi Huang and Jen-Chieh Liu, 國立台北大學
|
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79 |
PDF |
An Automated Synthesis Tool for Fully Differential OPAMPs
|
Cheng-Wu Lin and Soon-Jyh Chang, 國立成功大學
|
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80 |
PDF |
An Efficient BMCS Approach to Accurately Predict Process Variation Effects of PLL Circuits
|
Chin-Cheng Kuo, Meng-Jung Lee, I-Ching Tsai, Chien-Nan Jimmy Liu, and Ching-Ji
Huang, 國立中央大學 |
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81 |
PDF |
An Efficient Energy Modeling Approach for VLIW DSP at Instruction-Level
|
Wen-Tsan Hsieh, Hsin-Ying Liao, Chien-Nan Jimmy Liu, Shu-Yu Cheng, Ji-Jan
Chen, 國立中央大學 |
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82 |
PDF |
An Efficient Metric Normalization Architecture for High-speed Low-power Viterbi Decoder
|
Kelvin Yi-Tse Lai, 國立雲林科技大學 |
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83 |
PDF |
An Embedded 10-bit 200MHz DAC IP with Self-Calibrating Current Bias for SoC Applications
|
Chung-Ming Pan, Chien-Hung Tsai, 國立成功大學
|
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84 |
PDF |
An Experiment of Test Plan Construction & Test Automation
|
Tsung-Ju Yang1, Ming-Chang Tung1, Wei-Yu Lin1, Zhi-Wei Lin1, Chi-Hen Chang1, Farn
Wang1, 國立台灣大學 |
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85 |
PDF |
An Experimentation Suite for Education in Low-Noise Design
|
You-wei Liang, Shinyu Chen, Robert Rieger, 國立中山大學
|
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86 |
PDF |
An Integrated Spatial-Temporal Sampling Rate Conversion Architecture by Motion Compensation for TV Display
|
Chih-Hung Kuo, Li-Chuan Chang, Zheng-Wei Liu and Bin-Da
Liu, 國立成功大學 |
|
87 |
PDF |
An Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction Algorithm
|
Ya Wen Tsai, Yung Tai Chang, Jun Cheng Chi, Mely Chen Chi, 中原大學
|
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88 |
PDF |
An Ultra-low Power Multi-mode LDPC Decoder Chip for Mobile WiMAX System
|
Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin and An-Yeu (Andy) Wu, 國立台灣大學
|
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89 |
PDF |
Analog Circuits Fault Diagnosis under Parameter Variations Based on Fuzzy Logic system
|
林宗志,陳盈州,郭明仁, 逢甲大學 |
|
90 |
PDF |
Analytical Aerial Imaging Simulation for OPC
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陳中平,詹霖,曾俊貴,鍾士勇,王芝宇, 國立台灣大學 |
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91 |
PDF |
Analytical Synthesis of Low-Sensitivity Voltage-Mode Odd-Nth-Order OTA-C Elliptic Filter Structure with the Minimum Number of Components
|
Chun-Ming Chang, 中原大學 |
|
92 |
PDF |
Architecture of Adaptive Channel Equalizer in Dedicated Short Range Communication (DSRC) and Vehicle Infotainment Systems
|
Yong-Hua Cheng, Yi-Hung Lu, Chia-Ling Liu, 工業技術研究院
|
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93 |
PDF |
Area-Driven Decoupling Capacitance Allocation Based on Space Sensitivity Analysis
|
Jin-Tai Yan, Ming-Yuen Wu and Zhi-Wei Chen, 中華大學
|
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94 |
PDF |
Baseband OFDM Receiver Design for Fixed WiMAX Communication
|
Chi-chie Chang and Jen-Ming Wu, 國立清華大學
|
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95 |
PDF |
CMOS BANDGAP REFERENCE WITH CURVATURE COMPENSATION ON HIGHER ORDER TEMPERATURE TERMS
|
Hong-Yi Huang and Ru-Jie Wang, 國立台北大學
|
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96 |
PDF |
Combined Decoding and Flexible Transform Designs for Effective H.264/AVC Decoders
|
Yi-Chih Chao, Shih-Tse Wei, Jar-Ferr Yang and Bin-Da Liu, 國立成功大學
|
|
97 |
PDF |
Compact Dual-Core Architecture |
Jih-Ching Chiu and Yu-Liang Chou, 國立中山大學
|
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98 |
PDF |
Computation Sharing Programmable FIR Filter Using Canonic Signed Digit Representation
|
Shui-Wen Hsu; Yuan-Hao Huang, 國立清華大學
|
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99 |
PDF |
Configurable Hierarchical Decoder Architectures for H-QC LDPC Codes
|
Kuo-hsing Juan, Mong-kai Ku, Yu-min Chang, 國立台灣大學
|
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100 |
PDF |
Design a Hardware Interprocessor Communication Mechanism for a Multi-core Computer System
|
Slo-Li Chu, Chih-Chieh Hsiao, Pin-Hua Chiu, Hsien-Chang Lin, 中原大學
|
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101 |
PDF |
Design a Multiplicative type-II Fuzzy Cellular Neural Network with CMOS Image Sensor
|
Jui-Lin Lai, Yuan-Hung Lo, Yan-Ting Chen, and Rong-Jian Chen, 國立聯合大學
|
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102 |
PDF |
Design and Implementation of a Real-Time Global Tone Mapping Processor for
High Dynamic Range Video |
Tsun-Hsien Wang, Wei-Su Wong , Fang-Chu Chen, and Ching-Te
Chiu, 國立清華大學 |
|
103 |
PDF |
Design and Realization of Ultra Low-Capacitance Bond Pad With Inductive Compensation for RF Circuits in CMOS Technology
|
Yuan-Wen Hsiao, Chun-Yu Lin, and Ming-Dou Ker, 國立交通大學
|
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104 |
PDF |
Design of 1x2 MB-OFDM UWB Receiver with Channel Shortening Technique
|
Jen-Ming Wu and Hung-Wen Yang, 國立清華大學
|
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105 |
PDF |
Design of a 2X2 MIMO OFDM Transceiver With Correction of Different Carrier Frequency Offsets at Transmitter Antennas
|
Li-Wen Hsu and Dah-Chung Chang, 國立中央大學
|
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106 |
PDF |
Design of Low-Error Signed Fixed-Width Multipliers
|
Jiun-Ping Wang and Shiann-Rong Kuang, 國立中山大學
|
|
107 |
PDF |
DIAGNOSIS OF MULTIPLE SCAN CHAIN TIMING FAULTS
|
Wei-Shun Chuang, Wei-Chih Liu, and James
Chien-Mo Li, 國立台灣大學 |
|
108 |
PDF |
Differential Feed-forward Transconductor Design for High Linearity WiMax Subharmonic Mixer
|
Ying-Ta Lu, Hsien-Yuan Liao, Shao-Liang Lu, Joseph D. S. Deng*, and Hwann-Kaeo Chiou,
國立中央大學 |
|
109 |
PDF |
Don’t-Care Bits Filling for Reducing Capture Power
|
Wang-Dauh Tseng, Lung-Jen Lee, Chun-Kai Hsu, 元智大學
|
|
110 |
PDF |
Efficiency-Enhanced Multilevel LINC System Design
|
Kai-Yuan Jheng, Yuan-Jyue Chen, and An-Yeu
(Andy) Wu, 國立台灣大學 |
|
111 |
PDF |
Efficient Design of Graphic Rasterization Module
|
Chung-Hua Tsai, Yun-Nan Chang, 國立中山大學
|
|
112 |
PDF |
Efficient Fast Fourier Transform Processor Design for DVB-H System
|
Yu-Ju Cho, Chi-Li Yu, Tzu-Hao Yu, Cheng-Zhou Zhan and An-Yeu
(Andy) Wu, 國立台灣大學 |
|
113 |
PDF |
Energy-Efficient and High-Performance Power Gating in Microprocessor Functional Units
|
Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh, 國立中正大學
|
|
114 |
PDF |
Enhancing Compression Efficiency with Skewed-Probability Scan Chains
|
Sying-Jyan Wang, Shih-Cheng Chen, Katherine Shu-Min Li, 國立中興大學
|
|
115 |
PDF |
Frequency Domain Analog Circuit Fault Diagnosis Based on Radial Basis Function Neural Network
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林宗志,郭明仁,陳盈州, 逢甲大學 |
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116 |
PDF |
H.264 Decoder Optimization – VLIW DSP Platform
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Pou-Hang Ian, Jia-Ming Chen, Hsin-Wen Wei, Jian-Liang Luo, Wei-Kuan Shih,
國立清華大學 |
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117 |
PDF |
H.264/AVC Baseline Profile Decoder Optimization on PAC DSP
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Chiu-Ling Chen, Jia-Ming Chen, Jian-Liang Luo, Tien-Wei Hsieh ,Wei-Kuan
Shih, 國立清華大學 |
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118 |
PDF |
Hierarchical Decision Table for Bad Pixel Detection in Stereo Vision
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Tsung-Hsien Tsai, Nelson Yen-Chung Chang and Tian-Sheuan Chang, 國立交通大學
|
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119 |
PDF |
High Performance Decoder Design for Convolutional LDPC Codes
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Mu-Chung Chen, Jun-Wei Lin, Yen-Shuo Chang, Jin-Hao Yu, and Tzi-Dar Chiueh,
國立台灣大學 |
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120 |
PDF |
High Speed and Low Cost Implementations in Mix-Column/InvMix-Column
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Chung-Yi Li, Chih-Feng Chien, and Tsin-Yuan Chang, 國立清華大學
|
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121 |
PDF |
High Throughput Embedded Compression Engine for High-End LCD Applications
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Tsung-Han Tsai, Yu-Yu Lee, and Yu-Xuan
Lee, 國立中央大學 |
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122 |
PDF |
High-Quality Mipmapped Texture Compression
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Chih-Hao Sun and Shao-Yi Chien, 國立台灣大學
|
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123 |
PDF |
High-speed, Low Cost Parallel Memory-Based FFT Processors for OFDM Applications
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Shin-Yo Lin, Wei-Chien Tang, Muh-Tien Shiue, and Chin-Long Wey,
國立中央大學 |
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124 |
PDF |
HW/SW Co-Design of a Multi-Threaded Virtual Machine for a Scalable NoC Platform
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李昀隆, 陳泳超, 周哲民, 國立成功大學 |
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125 |
PDF |
Implementing an FPGA Baseband Multipath Fading Channel Emulator Using High-Level Modular Design
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Jeng-Kuang Hwang*, Kuei-Horng Lin, and Jeng-Da Li, Juinn-Horng Deng, 元智大學
|
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126 |
PDF |
Inductorless CMOS Receiver Front-End Circuits for 10-Gbs Optical Communications
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Chih-Hao Chen, 淡江大學 |
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127 |
PDF |
Limitation and Improvement of a Modified Precharge Phase Frequency Detector for Wireless Frequency Synthesizer Applications
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C.-J. Li, C.-B. Lo, S.-W. Li, T.-S. Horng, and K.-C. Peng,
國立中山大學 |
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128 |
PDF |
Lithography-Aware Routing with Predictive OPC Formulae
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Tai-Chen Chen, Guang-Wan Liao, and Yao-Wen
Chang, 國立台灣大學 |
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129 |
PDF |
Low Dropout Voltage Regulator with Current-Limit Circuit
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Chien-Cheng Chen, Nan-Xiong Huang, Miin-Shyue Shiau, Hong-Chong Wu, Don-Gey Liu, 逢甲大學
|
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130 |
PDF |
Low Power Sigma Delta Modulator with Dynamic Biasing for Audio Applications
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Hsin-Liang Chen, Yi-Sheng Lee, and Jen-Shiun Chiang, 淡江大學
|
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131 |
PDF |
MFASE Multiple Functions SoCs Analysis Environment
|
Ya-Shu Chen, Shih-Chun Chou, Chi-Sheng Shih and Tei-Wei Kuo,
國立台灣大學 |
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132 |
PDF |
Mismatch Address Index Encoding for Data Compression in Scan Test
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Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, and Hcc-Hang Jang, 元智大學
|
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133 |
PDF |
Mixed-Vth (MVT) CMOS Circuit Design For Low Power Cell Libraries
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Jyun-Yi Lin, Li-Rong Wang, Chia-Lin Hu and Shyh-Jye Jou,
國立交通大學 |
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134 |
PDF |
Modeling on the Mutual Inductance of On-Chip Transformers
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Heng-Ming Hsu, Sih-Han Lai and Hsien-Feng Liao, 國立中興大學
|
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135 |
PDF |
Modified Essential Spare Pivoting Algorithm for Embedded Memories
with Global Block-Based Redundancy |
Chun-Lin Yang and Shyue-Kung Lu, 輔仁大學
|
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136 |
PDF |
Multiple-Input XOR/XNOR Circuit Design Using Pass-Transistor Logic and Its Application in Cryptography
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Ming-Yu Tsai, Chia-Sheng Wen, and Shen-Fu
Hsiao, 國立中山大學 |
|
137 |
PDF |
New Low Supply-Bounce Current-Mode Shunt Regulator
|
Che-Min Kung, Chan-Min Pan, Jiann-Jong Chen, Yuh-Shyan Hwang and Wen-Ta Lee,
國立台北科技大學 |
|
138 |
PDF |
Non-Slicing Floorplanning-Based Crosstalk Reduction on Gridless Track Assignment
|
Win-Nai Zheng, Yu-Ning Zhang, and Yih-Lang
Li, 國立交通大學 |
|
139 |
PDF |
Novel Devices Merging RITD and CMOS for Future VLSI Use
|
Jyi-Tsong Lin, Wei-Chin Lin, Chao-Yu Hou,
國立中山大學 |
|
140 |
PDF |
Novel Low-Power Bus Coding Method for Crosstalk Noise Reduction
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Chia-Hao Fang and Chih-Peng Fan, 國立中興大學
|
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141 |
PDF |
Novel VLSI Design of Circular-Carry-Select (CCS) Based Diminished-One Modulo 2n+1 Adder
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Su-Hon Lin, Ming-Hwa Sheu, Kuang-Hui Wang, Jun-Jie Zhu and Si-Ying
Chen, 國立雲林科技大學 |
|
142 |
PDF |
Object-Oriented Hardware/Software Co-Design Using Java
|
Chin-Tai Chou, Fu-Chiung Cheng, Hung-Chi Wu, 大同大學
|
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143 |
PDF |
On Power-State-Aware Routing and Buffer Insertion
|
Ming-Hua Wu and Iris Hui-Ru Jiang, 國立交通大學
|
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144 |
PDF |
Optimal Redundant Via Insertion Using Mixed Integer Linear Programming
|
Kuang-Yao Lee, Ting-Chi Wang and Kai-Yuan Chao,
國立清華大學 |
|
145 |
PDF |
Performance Comparisons and Tradeoffs of Table-Based Arithmetic Function Evaluators
|
Ping-Chung Wei, Ching-Pin Lin, and Shen-Fu
Hsiao, 國立中山大學 |
|
146 |
PDF |
Performance Improvement using Application-Specific Instructions under Hardware Constrains
|
Chijie Lin, Jiying Wu, Jerung Shiu, Desheng Chen, Yiwen Wang, 逢甲大學
|
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147 |
PDF |
Post-Chip Adjustable Low Power Delay Element
|
Jung-Lin Yang, Chih-Wei Chao, 南台科技大學 |
|
148 |
PDF |
Power-Aware Memory Mapping for FPGAs
|
Tien-Yuan Hsu, Ting-Chi Wang, and Kuang-yao
Lee, 國立清華大學 |
|
149 |
PDF |
Q-Factor Behavior Study of 90-nm RF-CMOS Inductors Using Transmission-Line Mode
|
C.-H. Huang and T. -S. Horng, 國立中山大學
|
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150 |
PDF |
Reconfigurable Hardware Module Sequencer for Dynamically Partially Reconfigurable Systems
|
Chin-Chieh Hung and Pao-Ann Hsiung, 國立中正大學
|
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151 |
PDF |
Reduction of Power Dissipation during Scan Testing by Test Vector Ordering
|
Wang-Dauh Tseng, Lung-Jen Lee, 元智大學 |
|
152 |
PDF |
Register Processor for MMX instructions
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Jih-Ching Chiu, Shou-Xi Hong and Kai-Ming Yang, 國立中山大學
|
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153 |
PDF |
Reusing Cache for Real-Time Memory Address Trace Compression
|
Chung-Fu Kao, Chun-Hung Lai, and Ing-Jer
Huang, 國立中山大學 |
|
154 |
PDF |
Routability-Driven Track Routing for Coupling Capacitance Reduction
|
Jin-Tai Yan, Zhi-Wei Chen and Kuen-Ming Lin, 中華大學
|
|
155 |
PDF |
SAT Based Boolean Matching with Don't Cares
|
Kuo-Hua Wang and Chung-Ming Chan, 輔仁大學
|
|
156 |
PDF |
Self –Aligned Double Bits SONOS Cell and Its Memory Circuit Design
|
Jyi-Tsong Lin, Wei-Ching Lin, Ho-Lin Lee,
國立中山大學 |
|
157 |
PDF |
Self-Aware Medium-Grained Adaptive Power Control Using Current Monitoring Technique
|
Wei-Chih Hsieh and Wei Hwang, 國立交通大學
|
|
158 |
PDF |
SIMD Code Generation for Multimedia |
Cheng-Cho Jean1, Guang-Huei Lin1, Sao-Jie
Chen1, and Alan P. Su2, 國立台灣大學 |
|
159 |
PDF |
SIMD Optimizations for PAC VLIW DSP Processors with Sub-word Instructions
|
Ci-Bang Kuan, Jenq Kuen Lee, 國立清華大學 |
|
160 |
PDF |
Simultaneous Module Selection and Clock Skew Scheduling for Minimizing Standby Leakage Current
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Shih-Hsu Huang, Da-Chen Tzeng, Chun-Hua Cheng, 中原大學
|
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161 |
PDF |
Skip Control Algorithm of Motion Estimation for Power-scalable H.264 Video Encoder
|
Chieh Chien, Yu-Han Chen, and Liang-Gee
Chen, 國立台灣大學 |
|
162 |
PDF |
Stability Analysis of Fourth-Order Charge-Pump PLLs using Linearized Discrete-Time Models
|
Chia-Yu Yao, Chun-Te Hsu, Chih-Chun Hsieh, 國立台灣科技大學
|
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163 |
PDF |
Standard Cell Like Via-Configurable Logic Block Design for Structured ASICs
|
Mei-Chen Li, Chien-chung Lai, Hui-Hsiang Tung, Rung-Bin Lin, 元智大學
|
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164 |
PDF |
Sub-mW 5-GHz Receiver Front-End Circuit Design
|
Tatao Hsu, Yen-Lin Liu, Shu-Hui Yen, and Chien-Nan Kuo,
國立交通大學 |
|
165 |
PDF |
Symbol and Integer Carrier Frequency Offset Synchronization for IEEE802.16e
|
Juan-Nan Lin, Hsiao-Yun Chen and Shyh-Jye Jou,
國立交通大學 |
|
166 |
PDF |
Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture
|
Sying-Jyan Wang, Po-Chang Tsai, Hung-Ming Weng, Katherine Shu-Min Li, 國立中興大學
|
|
167 |
PDF |
Test Efficiency Analysis of SOC Test Platforms
|
Tong-Yu Hsieh, Kuen-Jong Lee and Jian-Jhih You, 國立成功大學
|
|
168 |
PDF |
Test Generation for Transition Delay and RS-CFM Faults in Modified Booth Multipliers
|
Hsing-Chung Liang and Pao-Hsin Huang, 中原大學
|
|
169 |
PDF |
Testing MRAM for Write Disturbance Fault
|
Wan-Yu Lo, Ching-Yi Chen, Chin-Lung Su, and Cheng-Wen Wu, 國立清華大學
|
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170 |
PDF |
The Efficient VLSI Design on BI-CUBIC Interpolation for Real Time Digital Image Scaling
|
林正基(Chung-chi Lin), 國立雲林科技大學 |
|
171 |
PDF |
Throughput-Aware Floorplanning by Considering Multiple Critical Cycles
|
Li-Ya Wang and Juinn-Dar Huang, 國立交通大學
|
|
172 |
PDF |
Topology Generation and Floorplanning for Low Power Application-Specific Network-on-Chips |
Wan-Yu Lee and Iris Hui-Ru Jiang, 國立交通大學
|
|
173 |
PDF |
Totally Self-Checking Borden Code Checker Design Using Modulo Adders
|
Wen-Feng Chang, Debaleena Das, Cheng-Wen Wu, 萬能科技大學
|
|
174 |
PDF |
Transimpedance Amplifier with Enlarged Input Capacitance Tolerance for Optical Receiver
|
Jiann-Jiun Lu and Chia-Ming Tsai, 國立交通大學
|
|
175 |
PDF |
Using Output-Clamped Amplifier to Implement Time-Based Interface Circuit for Measuring Tiny Grounded Capacitance
|
Wei-Hung Hsu and Meng-Lieh Sheu, 國立暨南國際大學
|
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176 |
PDF |
VLSI Implementation for Block-Based Gradient Domain High Dynamic Range Compression
|
Tsun Hsien Wang,Wei-Ming Ke,Chih-Hsueh Huang,Ding-Chuang Zwao,Fang-Chu Chen and Ching-Te
Chiu, 國立清華大學 |
|
177 |
PDF |
Voltage-Mode First Order All-Pass Filter using DDCC
|
Wei–Yuan Chiu , Jiun–Wei Horng and Chuan–Hsien Chang, 中原大學
|
|
178 |
PDF |
Yield Analysis for the 65nm SRAM Cells Design with Resolution Enhancement Techniques (RET)
|
J. J. Tang, C. L. Liao, P. C. Jheng, S. H. Chen, K. M. Lai, and L. J. Lin,, 南台科技大學
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