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1 |
PDF |
00070 |
Design and Realization of Ultra Low-Capacitance Bond Pad With Inductive Compensation for RF Circuits in CMOS Technology
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Yuan-Wen Hsiao, Chun-Yu Lin, and Ming-Dou Ker, 國立交通大學
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P1-4 |
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2 |
PDF |
00071 |
Stability Analysis of Fourth-Order Charge-Pump PLLs using Linearized Discrete-Time Models
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Chia-Yu Yao, Chun-Te Hsu, Chih-Chun Hsieh, 國立台灣科技大學
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P5-8 |
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3 |
PDF |
00073 |
A 5-bit 1 GSample/s Two-Stage ADC with a New Flash Folded Architecture
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Hung-Yu Huang, Ying-Zu Lin and Soon-Jyh Chang, 國立成功大學
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P9-12 |
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4 |
PDF |
00078 |
Novel VLSI Design of Circular-Carry-Select (CCS) Based Diminished-One Modulo 2n+1 Adder
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Su-Hon Lin, Ming-Hwa Sheu, Kuang-Hui Wang, Jun-Jie Zhu and Si-Ying
Chen, 國立雲林科技大學 |
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P13-16 |
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5 |
PDF |
00080 |
Frequency Domain Analog Circuit Fault Diagnosis Based on Radial Basis Function Neural Network
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林宗志,郭明仁,陳盈州, 逢甲大學 |
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P17-20 |
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6 |
PDF |
00081 |
A Single-Clock Enhanced Random Access Scan
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Chen-An Chen, Wei-Yi He and Tsung-Chu
Huang, 國立彰化師範大學 |
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P21-24 |
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7 |
PDF |
00083 |
Novel Low-Power Bus Coding Method for Crosstalk Noise Reduction
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Chia-Hao Fang and Chih-Peng Fan, 國立中興大學
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P25-28 |
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8 |
PDF |
00085 |
A Quarter-Rate 2.56/3.2Gbps 16/20:1 SERDES Interface in 0.18μm CMOS technology
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Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, YarSun Hsu, Ming-Hao Lu, Ping-Lin Yang, Fan-Ta Chen, You-Hung Li, Yu-Hao Hsu, Min-Sheng
Kao, 國立清華大學 |
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P29-32 |
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9 |
PDF |
00086 |
A RF CMOS Low Noise Amplifier Using High-Q Active Inductor Loads with Binary Code for Multi-Band Applications
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Jenn-Tzer Yang, Yuan-Hao Lee, Yi-Yuan Huang, Yu-Min Mu, and Yen-Ching Ho, 明新科技大學
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P33-36 |
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10 |
PDF |
00088 |
A Protocol-Reconfigurable Double-Layer External Memory Management for H.264/AVC Decoder
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Chang-Hsuan Chang, Ming-Hung Chang, and Wei Hwang, 國立交通大學
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P37-40 |
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11 |
PDF |
00090 |
Reconfigurable Hardware Module Sequencer for Dynamically Partially Reconfigurable Systems
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Chin-Chieh Hung and Pao-Ann Hsiung, 國立中正大學
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P41-44 |
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12 |
PDF |
00091 |
Simultaneous Module Selection and Clock Skew Scheduling for Minimizing Standby Leakage Current
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Shih-Hsu Huang, Da-Chen Tzeng, Chun-Hua Cheng, 中原大學
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P45-48 |
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13 |
PDF |
00092 |
Voltage-Mode First Order All-Pass Filter using DDCC
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Wei–Yuan Chiu , Jiun–Wei Horng and Chuan–Hsien Chang, 中原大學
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P49-52 |
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14 |
PDF |
00093 |
Area-Driven Decoupling Capacitance Allocation Based on Space Sensitivity Analysis
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Jin-Tai Yan, Ming-Yuen Wu and Zhi-Wei Chen, 中華大學
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P53-56 |
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15 |
PDF |
00094 |
A compact square-root domain filter
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Chia-Hsiung Kao, Ping-Yu Tsai, Wen-Pin Lin and Wan Chen Lo, 國立中山大學
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P57-60 |
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16 |
PDF |
00095 |
High-speed, Low Cost Parallel Memory-Based FFT Processors for OFDM Applications
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Shin-Yo Lin, Wei-Chien Tang, Muh-Tien Shiue, and Chin-Long Wey,
國立中央大學 |
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P61-65 |
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17 |
PDF |
00096 |
Self-Aware Medium-Grained Adaptive Power Control Using Current Monitoring Technique
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Wei-Chih Hsieh and Wei Hwang, 國立交通大學
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P66-69 |
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18 |
PDF |
00097 |
A Novel Precise Step-Shaped Soft-Start Technique for Integrated DC-DC Converter
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Yung-Chun Chuang and Ke-Horng Chen, 國立交通大學
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P70-73 |
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19 |
PDF |
00098 |
A Low Power Tree-Type Multiplexer with Embedded Timing Skew Switch
|
HungWen Lu, 國立中央大學 |
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P74-77 |
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20 |
PDF |
00099 |
A Energy-Efficient 256X144 TCAM Design
|
Wen-Yen Liu, Po-Tsang Huang, and Wei Hwang, 國立交通大學
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P78-81 |
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21 |
PDF |
00102 |
Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture
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Sying-Jyan Wang, Po-Chang Tsai, Hung-Ming Weng, Katherine Shu-Min Li, 國立中興大學
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P82-85 |
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22 |
PDF |
00103 |
A Low Jitter 2.5-GHz Self-Calibration PLL
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鄭國興、蔡玉章、洪凱尉, 國立中央大學 |
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P86-81 |
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23 |
PDF |
00104 |
An Integrated Spatial-Temporal Sampling Rate Conversion Architecture by Motion Compensation for TV Display
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Chih-Hung Kuo, Li-Chuan Chang, Zheng-Wei Liu and Bin-Da
Liu, 國立成功大學 |
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P90-93 |
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24 |
PDF |
00105 |
A CMOS Temperature Sensor Design for Implantable Bio-Medical Devices
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Ying-Hsiang Wang, Wen-Yaw Chung, Chiung-Cheng Chuang, Chien-Hsi Kao, 中原大學
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P94-97 |
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25 |
PDF |
00106 |
Topology Generation and Floorplanning for Low Power Application-Specific Network-on-Chips
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Wan-Yu Lee and Iris Hui-Ru Jiang, 國立交通大學
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P98-101 |
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26 |
PDF |
00107 |
A Partially Parallel Low-Density Parity Check Code Decoder with Reduced Memory for Long Code-Length
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Chin-Kuang Lian, Shin-Yo Lin, Tsung-Han Tsai, Chin-Long Wey, 國立中央大學
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P102-105 |
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27 |
PDF |
00108 |
A Dual Phase Charge Pump with Compact Size
|
Po-Chin Fan and Ke-Horng Chen, 國立交通大學
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P106-109 |
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28 |
PDF |
00110 |
On Power-State-Aware Routing and Buffer Insertion
|
Ming-Hua Wu and Iris Hui-Ru Jiang, 國立交通大學
|
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P110-113 |
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29 |
PDF |
00111 |
Architecture of Adaptive Channel Equalizer in Dedicated Short Range Communication (DSRC) and Vehicle Infotainment Systems
|
Yong-Hua Cheng, Yi-Hung Lu, Chia-Ling Liu, 工業技術研究院
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P114-117 |
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30 |
PDF |
00112 |
A Comparative Study of LNS and Floating-Point arithmetic
|
Chih-Yen Fan and Chi-Chyang Chen, 逢甲大學
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P118-121 |
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31 |
PDF |
00114 |
Low Dropout Voltage Regulator with Current-Limit Circuit
|
Chien-Cheng Chen, Nan-Xiong Huang, Miin-Shyue Shiau, Hong-Chong Wu, Don-Gey Liu, 逢甲大學
|
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P122-125 |
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32 |
PDF |
00115 |
SAT Based Boolean Matching with Don't Cares |
Kuo-Hua Wang and Chung-Ming Chan, 輔仁大學
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P126-129 |
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33 |
PDF |
00116 |
A self-oscillating switching power amplifier
|
Chia-Hsiung Kao, Ping-Yu Tsai, Wen-Pin Lin and Ming-Ching Chou, 國立中山大學
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P130-133 |
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34 |
PDF |
00122 |
The Efficient VLSI Design on BI-CUBIC Interpolation for Real Time Digital Image Scaling
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林正基(Chung-chi Lin), 國立雲林科技大學 |
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P134-137 |
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35 |
PDF |
00124 |
An Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction Algorithm
|
Ya Wen Tsai, Yung Tai Chang, Jun Cheng Chi, Mely Chen Chi, 中原大學
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P138-141 |
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36 |
PDF |
00126 |
A Dual-Mode Step-Up DC/DC Converter with Current-Limiting Technology
|
Chun-Ting Kuo, Wan-Rone Liou and Ping-Hsing Chen, 國立台灣海洋大學
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P142-145 |
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37 |
PDF |
00127 |
Q-Factor Behavior Study of 90-nm RF-CMOS Inductors Using Transmission-Line Mode
|
C.-H. Huang and T. -S. Horng, 國立中山大學
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P146-149 |
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38 |
PDF |
00128 |
Analog Circuits Fault Diagnosis under Parameter Variations Based on Fuzzy Logic system
|
林宗志,陳盈州,郭明仁, 逢甲大學 |
|
P150-153 |
|
39 |
PDF |
00129 |
Post-Chip Adjustable Low Power Delay Element
|
Jung-Lin Yang, Chih-Wei Chao, 南台科技大學 |
|
P154-157 |
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40 |
PDF |
00130 |
A CMOS Low-Noise Amplifier with Shunt-Peaking for 3-5GHz Ultra-Wideband Wireless System
|
Zhe-Yang Huang, Che-Cheng Huang, and Chung-Chih
Hung, 國立交通大學 |
|
P158-161 |
|
41 |
PDF |
00131 |
Energy-Efficient and High-Performance Power Gating in Microprocessor Functional Units
|
Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh, 國立中正大學
|
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P162-165 |
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42 |
PDF |
00132 |
A Topology-Based Construction for X-Architecture Clock Routing
|
Chia-Chun Tsai*, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, and Rong-Shue Hsiao, 南華大學
|
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P166-169 |
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43 |
PDF |
00135 |
A Network-Flow Based Algorithm for Digital Microfluidic Biochip Routing
|
Ping-Hung Yuh, Chia-Lin Yang, and Yao-Wen
Chang, 國立台灣大學 |
|
P170-173 |
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44 |
PDF |
00139 |
Novel Devices Merging RITD and CMOS for Future VLSI Use
|
Jyi-Tsong Lin, Wei-Chin Lin, Chao-Yu Hou,
國立中山大學 |
|
P174-177 |
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45 |
PDF |
00140 |
A Novel Look-up Table-Based Multiplication/Squaring Architecture for Cryptosystems over GF(2sup/m/)
|
Wen-Ching Lin, Jun-Hong Chen, and Ming-Der Shieh, National Cheng Kung University
|
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P178-181 |
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46 |
PDF |
00142 |
Don’t-Care Bits Filling for Reducing Capture Power
|
Wang-Dauh Tseng, Lung-Jen Lee, Chun-Kai Hsu, 元智大學
|
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P182-185 |
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47 |
PDF |
00143 |
Mismatch Address Index Encoding for Data Compression in Scan Test
|
Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, and Hcc-Hang Jang, 元智大學
|
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P186-189 |
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48 |
PDF |
00144 |
A Transitive-Closure-Graph-Based Macro Placement Algorithm
|
Hsin-Chen Chen, Yi-Lin Chuang, Zhe-Wei Jiang, and Yao-Wen Chang, 國立台灣大學
|
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P190-193 |
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49 |
PDF |
00145 |
Analytical Synthesis of Low-Sensitivity Voltage-Mode Odd-Nth-Order OTA-C Elliptic Filter Structure with the Minimum Number of Components
|
Chun-Ming Chang, 中原大學 |
|
P194-197 |
|
50 |
PDF |
00150 |
Design of Low-Error Signed Fixed-Width Multipliers
|
Jiun-Ping Wang and Shiann-Rong Kuang, 國立中山大學
|
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P198-201 |
|
51 |
PDF |
00151 |
A Novel VLSI Iterative Division Algorithm for Fast Quotient Generation
|
Tso-Bing Juang, 國立屏東商業技術學院 |
|
P202-205 |
|
52 |
PDF |
00153 |
A HQPM-Based Transmitter with Digital Predistortion Scheme for Enhancing Average Efficiency
|
C.-T. Chen, C.-J. Li, T.-S. Horng, J.-K. Jau,
J.-Y. Li, P.-K. Horng, D.-S. Deng, 國立中山大學 |
|
P206-209 |
|
53 |
PDF |
00154 |
Test Efficiency Analysis of SOC Test Platforms
|
Tong-Yu Hsieh, Kuen-Jong Lee and Jian-Jhih You, 國立成功大學
|
|
P210-213 |
|
54 |
PDF |
00156 |
Using Output-Clamped Amplifier to Implement Time-Based Interface Circuit for Measuring Tiny Grounded Capacitance
|
Wei-Hung Hsu and Meng-Lieh Sheu, 國立暨南國際大學
|
|
P214-217 |
|
55 |
PDF |
00157 |
An Ultra-low Power Multi-mode LDPC Decoder Chip for Mobile WiMAX System
|
Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin and An-Yeu (Andy) Wu, 國立台灣大學
|
|
P218-221 |
|
56 |
PDF |
00158 |
A Low Distortion Class-AB Power Amplifier With Active Tuning
|
Ro-Min Weng, Chi-Wen Tsai, and Kuen-Yi
Lin, 國立東華大學 |
|
P222-224 |
|
57 |
PDF |
00161 |
Transimpedance Amplifier with Enlarged Input Capacitance Tolerance for Optical Receiver
|
Jiann-Jiun Lu and Chia-Ming Tsai, 國立交通大學
|
|
P225-228 |
|
58 |
PDF |
00162 |
Routability-Driven Track Routing for Coupling Capacitance Reduction
|
Jin-Tai Yan, Zhi-Wei Chen and Kuen-Ming Lin, 中華大學
|
|
P229-232 |
|
59 |
PDF |
00164 |
A Novel High-Speed SOC Test Scheme Using Virtual TAMs
|
Jiann-Chyi Rau, Chien-Hsu Wu, Chung-Lin Wu, 淡江大學
|
|
P233-236 |
|
60 |
PDF |
00166 |
Totally Self-Checking Borden Code Checker Design Using Modulo Adders
|
Wen-Feng Chang, Debaleena Das, Cheng-Wen Wu, 萬能科技大學
|
|
P237-240 |
|
61 |
PDF |
00167 |
Reusing Cache for Real-Time Memory Address Trace Compression
|
Chung-Fu Kao, Chun-Hung Lai, and Ing-Jer
Huang, 國立中山大學 |
|
P241-244 |
|
62 |
PDF |
00168 |
Differential Feed-forward Transconductor Design for High Linearity WiMax Subharmonic Mixer
|
Ying-Ta Lu, Hsien-Yuan Liao, Shao-Liang Lu, Joseph D. S. Deng*, and Hwann-Kaeo Chiou,
國立中央大學 |
|
P245-248 |
|
63 |
PDF |
00169 |
Analytical Aerial Imaging Simulation for OPC
|
陳中平;詹霖;曾俊貴;鍾士勇;王芝宇, 國立台灣大學 |
|
P249-252 |
|
64 |
PDF |
00170 |
A CMOS-MEMS Frequency Adaptive Resonator with Multiple Electrostatic Electrodes Driving.
|
J. C. Chiou and L. J. Shieh, 國立交通大學 |
|
P253-256 |
|
65 |
PDF |
00172 |
Baseband OFDM Receiver Design for Fixed WiMAX Communication
|
Chi-chie Chang and Jen-Ming Wu, 國立清華大學
|
|
P257-260 |
|
66 |
PDF |
00173 |
A Novel Membership Function Approximation for Effective Digital Circuit Design of Neural Networks
|
Che-Wei Lin and Jeen-Shing Wang, 國立成功大學
|
|
P261-265 |
|
67 |
PDF |
00174 |
Lithography-Aware Routing with Predictive OPC Formulae
|
Tai-Chen Chen, Guang-Wan Liao, and Yao-Wen
Chang, 國立台灣大學 |
|
P266-269 |
|
68 |
PDF |
00175 |
Self –Aligned Double Bits SONOS Cell and Its Memory Circuit Design
|
Jyi-Tsong Lin, Wei-Ching Lin, Ho-Lin Lee,
國立中山大學 |
|
P270-273 |
|
69 |
PDF |
00176 |
Reduction of Power Dissipation during Scan Testing by Test Vector Ordering
|
Wang-Dauh Tseng, Lung-Jen Lee, 元智大學 |
|
P274-277 |
|
70 |
PDF |
00177 |
A 1-V CMOS Pseudo-Differential Amplifier
with Multiple Common Mode Stabilization
and Frequency Compensation Loops |
Meng-Hung Shen, Po-Hsiang Lan and Po-Chiun Huang, 國立清華大學
|
|
P278-281 |
|
71 |
PDF |
00178 |
A 1-V Fully Differential Amplifier with
Buffered Nested-Miller Compensation |
Li-Wen Wang, Meng-Hung Shen and Po-Chiun Huang, 國立清華大學
|
|
P282-285 |
|
72 |
PDF |
00179 |
Modeling on the Mutual Inductance of On-Chip Transformers
|
Heng-Ming Hsu, Sih-Han Lai and Hsien-Feng Liao, 國立中興大學
|
|
P286-289 |
|
73 |
PDF |
00182 |
A 1.76 uW, 0.9V, 8-bit Successive Approximation Register ADC with Fully-Differential Input Capability
|
謝宗殷 洪浩喬, 國立交通大學 |
|
P290-293 |
|
74 |
PDF |
00184 |
A 14-Bit Fourth-Order Sigma-Delta Modulator with Feedforward Architecture for Hearing Aid
|
Shuenn-Yuh Lee, Jia-Hua Hong, Chi-Ching Lin, Chui-Kum Chiu, and Sheng-Jing Ku, 國立中正大學
|
|
P294-297 |
|
75 |
PDF |
00185 |
Computation Sharing Programmable FIR Filter Using Canonic Signed Digit Representation
|
Shui-Wen Hsu; Yuan-Hao Huang, 國立清華大學
|
|
P298-301 |
|
76 |
PDF |
00186 |
A Mini Stereo Digital Audio Processor Design
|
Po-Yu Kuo, Dian Zhou, Zhi-Ming Lin,, 德州大學達拉斯分校
|
|
P302-305 |
|
77 |
PDF |
00188 |
A Low Power 1V 10-bit Successive Approximation ADC
|
Yi-Hung Chen, Wan-Tin Lin and Hwang-Cherng Chow, 長庚大學
|
|
P306-309 |
|
78 |
PDF |
00189 |
Optimal Redundant Via Insertion Using Mixed Integer Linear Programming
|
Kuang-Yao Lee, Ting-Chi Wang and Kai-Yuan Chao,
國立清華大學 |
|
P310-313 |
|
79 |
PDF |
00190 |
A UWB CMOS Power Amplifier With Differential to Single-Ended Converter
|
Shuenn-Yuh Lee and Guan-Da Lu, 國立中正大學
|
|
P314-317 |
|
80 |
PDF |
00192 |
A Novel Architecture for Self-Reconfigurable Systems
|
Trong-Yen Lee, Yung-Lin Hsu, Che-Cheng Hu, 國立台北科技大學
|
|
P318-321 |
|
81 |
PDF |
00194 |
A DPA-Resistant AES Encryption Hardware Module
|
Kuan Jen Lin, Shih Hsien Yang and Chih Hsuan Hsu,
輔仁大學 |
|
P322-325 |
|
82 |
PDF |
00195 |
A Low-Complex Image Coding Algorithm Based on Wavelet Transform
|
Trong-Yen Lee, Yang-Hsin Fan and Su-Zhen Hong, 國立台北科技大學
|
|
P326-329 |
|
83 |
PDF |
00197 |
Limitation and Improvement of a Modified Precharge Phase Frequency Detector for Wireless Frequency Synthesizer Applications
|
C.-J. Li, C.-B. Lo, S.-W. Li, T.-S. Horng, and K.-C. Peng,
國立中山大學 |
|
P330-333 |
|
84 |
PDF |
00198 |
Design of 1x2 MB-OFDM UWB Receiver with Channel Shortening Technique
|
Jen-Ming Wu and Hung-Wen Yang, 國立清華大學
|
|
P334-337 |
|
85 |
PDF |
00199 |
An Experiment of Test Plan Construction & Test Automation
|
Tsung-Ju Yang1, Ming-Chang Tung1, Wei-Yu Lin1, Zhi-Wei Lin1, Chi-Hen Chang1, Farn
Wang1, 國立台灣大學 |
|
P338-342 |
|
86 |
PDF |
00200 |
A Flip-Flop Replacement Technique for IR Drop Reduction
|
Jiun-Kuan Wu, Liang-Ying Lu, Kuang-Yao Chen,Tsung-Yi Wu, 國立彰化師範大學
|
|
P343-346 |
|
87 |
PDF |
00202 |
A Timing-Driven X-Architecture Router with Obstacles
|
Shu-Ping Chang, Hsin Hsiung Huang,
Yu-Cheng Lin, and Tsai Ming Hsieh, 國立台東大學 |
|
P347-350 |
|
88 |
PDF |
00204 |
A 3.1–10.6 GHz Ultra-Wideband CMOS Low Noise Amplifier Using Bridged-Shunt-Series Peaking Technique
|
Yu-Liang Lin, Feng-Lin Shiu, and Hwann-Kaeo Chiou,
國立中央大學 |
|
P351-354 |
|
89 |
PDF |
00205 |
A Low-Hardware-Cost Logical OR Operation Log-SPA LDPC Decoder
|
Ming-Yu Lin, Ching-Da Chan, Jung-Chieh Chen, Po-Hui Yang, 國立雲林科技大學
|
|
P355-358 |
|
90 |
PDF |
00206 |
A Low-Complexity High-Performance Two-Dimensional
Look-Up Table for LDPC Hardware Implementation |
Tzu-Wen Chung, Chen-Pang Chang, Jung-Chieh Chen, Po-Hui Yang, 國立高雄師範大學
|
|
P359-362 |
|
91 |
PDF |
00207 |
A 8-BIT 150-MS/S FULLY DIFFERENTIAL DUAL-CHANNEL TIME-INTERLEAVED PIPELINE A/D CONVERTER
|
Chih-Hsiang Chang and Ching-Yuan Yang, 國立中興大學
|
|
P363-366 |
|
92 |
PDF |
00208 |
A Wide-Band Low-Power Quadrature VCO
|
Ching-Yi Chen, 國立中正大學 |
|
P367-370 |
|
93 |
PDF |
00212 |
A High-Resolution All-Digital Phase-Locked Loop with its Application to Built-In Speed Grading for Memory
|
Hsuan-Jung Hsu, Chun-Chieh Tu, and Shi-Yu Huang , 國立清華大學
|
|
P371-374 |
|
94 |
PDF |
00214 |
New Low Supply-Bounce Current-Mode Shunt Regulator
|
Che-Min Kung, Chan-Min Pan, Jiann-Jong Chen, Yuh-Shyan Hwang and Wen-Ta Lee,
國立台北科技大學 |
|
P375-378 |
|
95 |
PDF |
00216 |
CMOS BANDGAP REFERENCE WITH CURVATURE COMPENSATION ON HIGHER ORDER TEMPERATURE TERMS
|
Hong-Yi Huang and Ru-Jie Wang, 國立台北大學
|
|
P379-382 |
|
96 |
PDF |
00217 |
All-Digital PLL Using Bulk-Controlled Varactor and Pulse-Based DCO
|
Hong-Yi Huang and Jen-Chieh Liu, 國立台北大學
|
|
P383-386 |
|
97 |
PDF |
00219 |
A Scalable Graph-cut Engine Architecture for Real-time Vision
|
Nelson Yen-Chung Chang, Tian-Sheuan Chang,
國立交通大學 |
|
P387-390 |
|
98 |
PDF |
00220 |
A Redundancy Detection Algorithm for DCT and Quantization in H.264 Video Encoding
|
Ting-Wei Chen, Chang-Hsin Cheng, Yu Liu, Chun-Lung Hsu, 國立東華大學
|
|
P391-394 |
|
99 |
PDF |
00221 |
Throughput-Aware Floorplanning by Considering Multiple Critical Cycles
|
Li-Ya Wang and Juinn-Dar Huang, 國立交通大學
|
|
P395-398 |
|
100 |
PDF |
00222 |
Hierarchical Decision Table for Bad Pixel Detection in Stereo Vision
|
Tsung-Hsien Tsai, Nelson Yen-Chung Chang and Tian-Sheuan Chang, 國立交通大學
|
|
P399-402 |
|
101 |
PDF |
00223 |
A Multi-Code Rate IEEE 802.16e LDPC Decoder Design
|
Chih-Hao Hsiao and Yun-Nan Chang, 國立中山大學
|
|
P403-406 |
|
102 |
PDF |
00224 |
Skip Control Algorithm of Motion Estimation for Power-scalable H.264 Video Encoder
|
Chieh Chien, Yu-Han Chen, and Liang-Gee
Chen, 國立台灣大學 |
|
P407-410 |
|
103 |
PDF |
00225 |
An Efficient Metric Normalization Architecture for High-speed Low-power Viterbi Decoder
|
Kelvin Yi-Tse Lai, 國立雲林科技大學 |
|
P411-414 |
|
104 |
PDF |
00227 |
Efficiency-Enhanced Multilevel LINC System Design
|
Kai-Yuan Jheng, Yuan-Jyue Chen, and An-Yeu
(Andy) Wu, 國立台灣大學 |
|
P415-418 |
|
105 |
PDF |
00230 |
Enhancing Compression Efficiency with Skewed-Probability Scan Chains
|
Sying-Jyan Wang, Shih-Cheng Chen, Katherine Shu-Min Li, 國立中興大學
|
|
P419-422 |
|
106 |
PDF |
00233 |
VLSI Implementation for Block-Based Gradient Domain High Dynamic Range Compression
|
Tsun Hsien Wang,Wei-Ming Ke,Chih-Hsueh Huang,Ding-Chuang Zwao,Fang-Chu Chen and Ching-Te
Chiu, 國立清華大學 |
|
P423-426 |
|
107 |
PDF |
00235 |
Low Power Sigma Delta Modulator with Dynamic Biasing for Audio Applications
|
Hsin-Liang Chen, Yi-Sheng Lee, and Jen-Shiun Chiang, 淡江大學
|
|
P427-430 |
|
108 |
PDF |
00236 |
Design and Implementation of a Real-Time Global Tone Mapping Processor for
High Dynamic Range Video |
Tsun-Hsien Wang, Wei-Su Wong , Fang-Chu Chen, and Ching-Te
Chiu, 國立清華大學 |
|
P431-434 |
|
109 |
PDF |
00237 |
An Efficient BMCS Approach to Accurately Predict Process Variation Effects of PLL Circuits
|
Chin-Cheng Kuo, Meng-Jung Lee, I-Ching Tsai, Chien-Nan Jimmy Liu, and Ching-Ji
Huang, 國立中央大學 |
|
P435-438 |
|
110 |
PDF |
00240 |
Test Generation for Transition Delay and RS-CFM Faults in Modified Booth Multipliers
|
Hsing-Chung Liang and Pao-Hsin Huang, 中原大學
|
|
P439-442 |
|
111 |
PDF |
00241 |
A Scalable Frame-Pipeline Motion Estimation Processor for Full-Search Algorithm
|
Yeong-Kang Lai, Lien-Fei Chen, Yin-Ruey Huang, and Sheng-Yu Huang, 國立中興大學
|
|
P443-446 |
|
112 |
PDF |
00242 |
DIAGNOSIS OF MULTIPLE SCAN CHAIN TIMING FAULTS
|
Wei-Shun Chuang, Wei-Chih Liu, and James
Chien-Mo Li, 國立台灣大學 |
|
P447-450 |
|
113 |
PDF |
00243 |
A SAR-Based Smart Temperature Sensor with Binary-Weighted Search Algorithm
|
Chun-Chi Chen, Poki Chen, and Kai-Ming Wang, 國立台灣科技大學
|
|
P451-454 |
|
114 |
PDF |
00244 |
A Novel Infrared Tracking System with Winner-Take-All Implementation
|
Po-Hsiang Chang, Chih-Hsiung Shen, National Changhua University of Education
|
|
P455-458 |
|
115 |
PDF |
00245 |
Mixed-Vth (MVT) CMOS Circuit Design For Low Power Cell Libraries
|
Jyun-Yi Lin, Li-Rong Wang, Chia-Lin Hu and Shyh-Jye Jou,
國立交通大學 |
|
P459-462 |
|
116 |
PDF |
00246 |
A New Multi-Function Wave Generator Based on Multiple-Output Second-Generation Current Conveyors
|
Yuh-Shyan Hwang, Yu-Wen Chen, Jiann-Jong Chen, Wen-Ta Lee, 國立台北科技大學
|
|
P463-466 |
|
117 |
PDF |
00247 |
A Low Power Wide Range Duty Cycle Corrector Based on Pulse Shrinking/Stretching Mechanism
|
Poki Chen, Shi-Wei Chen, Juan-Shan Lai, 國立台灣科技大學
|
|
P467-470 |
|
118 |
PDF |
00248 |
A New Current-Mode Wheatstone Bridge Based on Fully Differential Operational Transresistance Amplifiers
|
Yuh-Shyan Hwang, Chun-Chi Shih, Jiann-Jong Chen, Wen-Ta Lee, 國立台北科技大學
|
|
P471-474 |
|
119 |
PDF |
00249 |
A Temperature-Compensation CMOS Subbandgap Reference with 1V Power Supply Operation
|
Hung-Wei Chen, Jing-Yu Luo, Wen-Cheng Yen, 國立聯合大學
|
|
P475-478 |
|
120 |
PDF |
00251 |
A Simulation-based Redundancy Identification in Combinational Circuits
|
Yi-Yuan Huang, Chun-Yao Wang, 國立清華大學
|
|
P479-482 |
|
121 |
PDF |
00252 |
A 0.8V SOP-Based Wideband Fourth-Order Cascade Delta-Sigma Modulator
|
Chien-Hung Kuo, and Shuo-Chau Chen, 淡江大學
|
|
P483-486 |
|
122 |
PDF |
00256 |
A New Self-Oscillating CMOS DC-DC Converter with Adaptive Mode-Switching Mechanism
|
Sau-Mou Wu , Chung-Lin Wu and Chia-Hsien Chang, 元智大學
|
|
P487-490 |
|
123 |
PDF |
00257 |
Non-Slicing Floorplanning-Based Crosstalk Reduction on Gridless Track Assignment
|
Win-Nai Zheng, Yu-Ning Zhang, and Yih-Lang
Li, 國立交通大學 |
|
P491-494 |
|
124 |
PDF |
00259 |
A Novel Log-Lin-Log Response CMOS Image Sensor with High Swing and Wide Dynamic Range
|
Sau-Mou Wu and Ming-Wei Chen, 元智大學
|
|
P495-498 |
|
125 |
PDF |
00260 |
Configurable Hierarchical Decoder Architectures for H-QC LDPC Codes
|
Kuo-hsing Juan, Mong-kai Ku, Yu-min Chang, 國立台灣大學
|
|
P499-502 |
|
126 |
PDF |
00261 |
High-Quality Mipmapped Texture Compression
|
Chih-Hao Sun and Shao-Yi Chien, 國立台灣大學
|
|
P503-506 |
|
127 |
PDF |
00262 |
A Design Methodology for Application-Specific Instruction-set Processors with Memory Access Considerations
|
Ji-Ying Wu, Chi-Jie Lin, Je-Rung Shiu, De-Sheng Chen, Yi-Wen Wang, 逢甲大學
|
|
P507-510 |
|
128 |
PDF |
00263 |
An Experimentation Suite for Education in Low-Noise Design
|
You-wei Liang, Shinyu Chen, Robert Rieger, 國立中山大學
|
|
P511-514 |
|
129 |
PDF |
00264 |
Sub-mW 5-GHz Receiver Front-End Circuit Design
|
Tatao Hsu, Yen-Lin Liu, Shu-Hui Yen, and Chien-Nan Kuo,
國立交通大學 |
|
P515-518 |
|
130 |
PDF |
00265 |
SIMD Code Generation for Multimedia
|
Cheng-Cho Jean1, Guang-Huei Lin1, Sao-Jie
Chen1, and Alan P. Su2, 國立台灣大學 |
|
P519-522 |
|
131 |
PDF |
00266 |
A Wide-Range Synchronous 50% Duty-Cycle Clock Generator
|
Wei-Hao Chiu and Tsung-Hsien Lin, 國立台灣大學
|
|
P523-526 |
|
132 |
PDF |
00268 |
An Efficient Energy Modeling Approach for VLIW DSP at Instruction-Level
|
Wen-Tsan Hsieh, Hsin-Ying Liao, Chien-Nan Jimmy Liu, Shu-Yu Cheng, Ji-Jan
Chen, 國立中央大學 |
|
P527-530 |
|
133 |
PDF |
00269 |
An Embedded 10-bit 200MHz DAC IP with Self-Calibrating Current Bias for SoC Applications
|
Chung-Ming Pan, Chien-Hung Tsai, 國立成功大學
|
|
P531-534 |
|
134 |
PDF |
00271 |
High Performance Decoder Design for Convolutional LDPC Codes
|
Mu-Chung Chen, Jun-Wei Lin, Yen-Shuo Chang, Jin-Hao Yu, and Tzi-Dar Chiueh,
國立台灣大學 |
|
P535-538 |
|
135 |
PDF |
00272 |
Implementing an FPGA Baseband Multipath Fading Channel Emulator Using High-Level Modular Design
|
Jeng-Kuang Hwang*, Kuei-Horng Lin, and Jeng-Da Li, Juinn-Horng Deng, 元智大學
|
|
P539-542 |
|
136 |
PDF |
00275 |
H.264 Decoder Optimization – VLIW DSP Platform
|
Pou-Hang Ian, Jia-Ming Chen, Hsin-Wen Wei, Jian-Liang Luo, Wei-Kuan Shih,
國立清華大學 |
|
P543-548 |
|
137 |
PDF |
00276 |
H.264/AVC Baseline Profile Decoder Optimization on PAC DSP
|
Chiu-Ling Chen, Jia-Ming Chen, Jian-Liang Luo, Tien-Wei Hsieh ,Wei-Kuan
Shih, 國立清華大學 |
|
P549-552 |
|
138 |
PDF |
00280 |
Design a Multiplicative type-II Fuzzy Cellular Neural Network with CMOS Image Sensor
|
Jui-Lin Lai, Yuan-Hung Lo, Yan-Ting Chen, and Rong-Jian Chen, 國立聯合大學
|
|
P553-556 |
|
139 |
PDF |
00281 |
A Conditional Isolation Technique for Low-Power and High-speed Wide Domino Gates
|
Wei-Hao Chiu and How-Rern Lin, 大葉大學 |
|
P557-560 |
|
140 |
PDF |
00282 |
A Simple Yet Efficient Global Router with Mirrored Monotonic Routing and Reduced Multi-Source Multi-Sink Maze Routing
|
Ke-Ren Dai, Jyun-Yi Lin, and Yih-Lang Li,
國立交通大學 |
|
P561-564 |
|
141 |
PDF |
00284 |
HW/SW Co-Design of a Multi-Threaded Virtual Machine for a Scalable NoC Platform
|
李昀隆, 陳泳超, 周哲民, 國立成功大學 |
|
P565-568 |
|
142 |
PDF |
00287 |
Yield Analysis for the 65nm SRAM Cells Design with Resolution Enhancement Techniques (RET)
|
J. J. Tang, C. L. Liao, P. C. Jheng, S. H. Chen, K. M. Lai, and L. J. Lin,, 南台科技大學
|
|
P569-572 |
|
143 |
PDF |
00288 |
Adaptive Sensing Control in SRAM Design Using Per-Column Timing Tracking Scheme
|
Ya-Chun Lai, Ming-Yi Chang, and Shi-Yu Huang, 國立清華大學
|
|
P573-576 |
|
144 |
PDF |
00293 |
SIMD Optimizations for PAC VLIW DSP Processors with Sub-word Instructions
|
Ci-Bang Kuan, Jenq Kuen Lee, 國立清華大學 |
|
P577-580 |
|
145 |
PDF |
00294 |
Performance Improvement using Application-Specific Instructions under Hardware Constrains
|
Chijie Lin, Jiying Wu, Jerung Shiu, Desheng Chen, Yiwen Wang, 逢甲大學
|
|
P581-584 |
|
146 |
PDF |
00295 |
A Scalable Wavelet Image Coder Based on Zero-block and Array and Its Hardware Implementation |
Yuan-Long Jeang, Hung-Yu Wang, Cyuan-Cheng Wong, 崑山科技大學
|
|
P585-588 |
|
147 |
PDF |
00297 |
Design a Hardware Interprocessor Communication Mechanism for a Multi-core Computer System
|
Slo-Li Chu, Chih-Chieh Hsiao, Pin-Hua Chiu, Hsien-Chang Lin, 中原大學
|
|
P589-592 |
|
148 |
PDF |
00299 |
Power-Aware Memory Mapping for FPGAs
|
Tien-Yuan Hsu, Ting-Chi Wang, and Kuang-yao
Lee, 國立清華大學 |
|
P593-596 |
|
149 |
PDF |
00300 |
Testing MRAM for Write Disturbance Fault
|
Wan-Yu Lo, Ching-Yi Chen, Chin-Lung Su, and Cheng-Wen Wu, 國立清華大學
|
|
P597-600 |
|
150 |
PDF |
00301 |
Symbol and Integer Carrier Frequency Offset Synchronization for IEEE802.16e
|
Juan-Nan Lin, Hsiao-Yun Chen and Shyh-Jye Jou,
國立交通大學 |
|
P601-604 |
|
151 |
PDF |
00307 |
High Throughput Embedded Compression Engine for High-End LCD Applications
|
Tsung-Han Tsai, Yu-Yu Lee, and Yu-Xuan
Lee, 國立中央大學 |
|
P605-608 |
|
152 |
PDF |
00308 |
A 2.4GHz Current-reused VCO with Degenerated Resistors
|
Ruey-Lue Wang, Guo-Ruey Tsai , Yu-Feng Lin, YuJo Tzeng, 崑山科技大學
|
|
P609-611 |
|
153 |
PDF |
00310 |
MFASE Multiple Functions SoCs Analysis Environment
|
Ya-Shu Chen, Shih-Chun Chou, Chi-Sheng Shih and Tei-Wei Kuo,
國立台灣大學 |
|
P612-615 |
|
154 |
PDF |
00311 |
A Low Voltage Full-band Cascoded UWB LNA
|
Ruey-Lue Wang, Min-Chhuien Lin, Zhi-Cheng Lin, 崑山科技大學
|
|
P616-619 |
|
155 |
PDF |
00312 |
High Speed and Low Cost Implementations in Mix-Column/InvMix-Column
|
Chung-Yi Li, Chih-Feng Chien, and Tsin-Yuan Chang, 國立清華大學
|
|
P620-623 |
|
156 |
PDF |
00315 |
A Low-Power High-Gain Rail-to-Rail Input/Output Operational Amplifier
|
Chien-Hung Kuo, Hwa-Ming Lu, and Wei-Hsien Fang, 淡江大學
|
|
P624-627 |
|
157 |
PDF |
00316 |
A Novel Low Complexity Pulse-Triggered Flip-Flop Design with Dual Triggering Mode
|
Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu and Wei-Rong Ciou, 國立中興大學
|
|
P628-631 |
|
158 |
PDF |
00320 |
A HIGH PERFORMANCE CAVLC DECODER USING NON-ZERO SKIP AND MULTI-LEVEL DECODING
|
Tsung-Han Tsai and De-Lung Fang, 國立中央大學
|
|
P632-635 |
|
159 |
PDF |
00321 |
An Automated Synthesis Tool for Fully Differential OPAMPs
|
Cheng-Wu Lin and Soon-Jyh Chang, 國立成功大學
|
|
P636-639 |
|
160 |
PDF |
00324 |
Standard Cell Like Via-Configurable Logic Block Design for Structured ASICs
|
Mei-Chen Li, Chien-chung Lai, Hui-Hsiang Tung, Rung-Bin Lin, 元智大學
|
|
P640-643 |
|
161 |
PDF |
00326 |
Combined Decoding and Flexible Transform Designs for Effective H.264/AVC Decoders
|
Yi-Chih Chao, Shih-Tse Wei, Jar-Ferr Yang and Bin-Da Liu, 國立成功大學
|
|
P644-647 |
|
162 |
PDF |
00327 |
A Novel Design for Computation of All Transforms in H.264/AVC Decoders
|
Yi-Chih Chao, Hui-Hsien Tsai, Yu-Hsiu Lin, Jar-Ferr Yang, and Bin-Da Liu, 國立成功大學
|
|
P648-651 |
|
163 |
PDF |
00328 |
A Low-jitter Phase-rotation Spread Spectrum Clock Generator
for Serial ATA 6Gbps Clock and Data Recovery
|
Chi- Hsien Lin, Yen-Ying Huang, Shu-Rung Li, Yuan-Pu Cheng and Shyh- Jye Jou,
國立交通大學 |
|
P652-655 |
|
164 |
PDF |
00335 |
A 2.5 Gbps CMOS Fully Integrated Optical Receicer with Lateral PIN Detector
|
Wei-Zen Chen and Shih-Hao Huang, 國立交通大學
|
|
P656-659 |
|
165 |
PDF |
00338 |
Design of a 2X2 MIMO OFDM Transceiver With Correction of Different Carrier Frequency Offsets at Transmitter Antennas
|
Li-Wen Hsu and Dah-Chung Chang, 國立中央大學
|
|
P660-663 |
|
166 |
PDF |
00351 |
A Novel CMOS Smart Temperature Sensor for On-Line Thermal Monitoring
|
Wei-Cheng Lee, Hung-Chih Lin, and Tsin-Yuan
Chang, 國立清華大學 |
|
P664-667 |
|
167 |
PDF |
00359 |
6 Gb/s Digitally Phase Adjusted Clock Data Recovery for Spread Spectrum Clock
|
Chin-Hsien Lin, Yuan-Pu Cheng, Yen-Ying Huang and Shyh-Jye Jou,
國立交通大學 |
|
P668-671 |
|
168 |
PDF |
00360 |
80-S/s Delta Sigma Modulators For IR Thermometer
|
Jen-Shiun Chiang, Hsin-Liang Chen, Yao-Tsung Chang, and Meng-Hsuan Ho, 淡江大學
|
|
P672-675 |
|
169 |
PDF |
00361 |
Inductorless CMOS Receiver Front-End Circuits for 10-Gbs Optical Communications
|
Chih-Hao Chen, 淡江大學 |
|
P676-679 |
|
170 |
PDF |
00362 |
Object-Oriented Hardware/Software Co-Design Using Java
|
Chin-Tai Chou, Fu-Chiung Cheng, Hung-Chi Wu, 大同大學
|
|
P680-683 |
|
171 |
PDF |
00363 |
Efficient Fast Fourier Transform Processor Design for DVB-H System
|
Yu-Ju Cho, Chi-Li Yu, Tzu-Hao Yu, Cheng-Zhou Zhan and An-Yeu
(Andy) Wu, 國立台灣大學 |
|
P684-687 |
|
172 |
PDF |
00365 |
A Top-down, Mixed-level Design Methodology for CT BP ΔΣ Modulator Using Verilog-A
|
Hung-Yuan Chu #1, Chien-Hung Tsai #2, 國立成功大學
|
|
P688-691 |
|
173 |
PDF |
00366 |
Compact Dual-Core Architecture
|
Jih-Ching Chiu and Yu-Liang Chou, 國立中山大學
|
|
P692-695 |
|
174 |
PDF |
00368 |
Register Processor for MMX instructions
|
Jih-Ching Chiu, Shou-Xi Hong and Kai-Ming Yang, 國立中山大學
|
|
P696-700 |
|
175 |
PDF |
00369 |
Performance Comparisons and Tradeoffs of Table-Based Arithmetic Function Evaluators
|
Ping-Chung Wei, Ching-Pin Lin, and Shen-Fu
Hsiao, 國立中山大學 |
|
P701-704 |
|
176 |
PDF |
00370 |
Multiple-Input XOR/XNOR Circuit Design Using Pass-Transistor Logic and Its Application in Cryptography
|
Ming-Yu Tsai, Chia-Sheng Wen, and Shen-Fu
Hsiao, 國立中山大學 |
|
P705-708 |
|
177 |
PDF |
00373 |
Modified Essential Spare Pivoting Algorithm for Embedded Memories
with Global Block-Based Redundancy |
Chun-Lin Yang and Shyue-Kung Lu, 輔仁大學
|
|
P709-712 |
|
178 |
PDF |
00374 |
Efficient Design of Graphic Rasterization Module
|
Chung-Hua Tsai, Yun-Nan Chang, 國立中山大學
|
|
P713-716 |